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E-Ink Magic Calendar that automatically syncs to Google Calendar and runs off a battery powered Raspberry Pi Zero

Python 3,102 108 Updated Mar 1, 2024

Fast and memory-efficient exact attention

Python 13,448 1,226 Updated Sep 20, 2024

Building blocks for foundation models.

352 13 Updated Jan 3, 2024

Inference Llama 2 in one file of pure C

C 17,170 2,042 Updated Aug 6, 2024

Tensor library for machine learning

C++ 10,874 1,000 Updated Sep 20, 2024

Port of OpenAI's Whisper model in C/C++

C 34,523 3,519 Updated Sep 20, 2024

a lightweight LLM model inference framework

C++ 681 84 Updated Apr 7, 2024

LLM inference in C/C++

C++ 65,162 9,338 Updated Sep 20, 2024

LLM training in simple, raw C/CUDA

Cuda 23,338 2,601 Updated Sep 17, 2024

256-bit vector processor based on the RISC-V vector (V) extension

SystemVerilog 26 3 Updated May 1, 2021
SystemVerilog 8 1 Updated Sep 27, 2022

HYDRA: a multi-core RISC-V with cryptographically useful modes of operation

Verilog 6 2 Updated Jun 22, 2022

TinyLlama on Cortex-M55 using CMSIS-DSP and Helium vector instructions

C 5 1 Updated Sep 20, 2024

OpenBMC Distribution

BitBake 1,841 904 Updated Sep 19, 2024

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Tcl 820 187 Updated Aug 30, 2024

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

C++ 1,282 77 Updated Sep 10, 2024

A minimal TCP/IP stack

C 483 11 Updated Mar 28, 2024
Verilog 3 Updated Apr 5, 2024

In this project I wrote a database management system with C language, which can operate the commands of SQL and guarantee proper output at the same time.

C 8 2 Updated Dec 14, 2017

❄️ Visual editor for open FPGA boards

JavaScript 1,694 244 Updated Aug 30, 2024

An easy and fast way to create a Python GUI 🐍

Python 8,988 824 Updated Aug 21, 2024

A scalable High-Level Synthesis framework on MLIR

MLIR 217 45 Updated May 15, 2024

A tool for configuring Xilinx Spartan 3 FPGAs via FT232H-based USB-to-JTAG adapter

C++ 16 4 Updated Dec 31, 2020

A tiny Open POWER ISA softcore written in VHDL 2008

Verilog 653 98 Updated Aug 17, 2024