ricv-ml
project contains FPGA prototype of functional RISCV core able to :
- run Linux rootfs build with riscv toolchain ( from
SDCARD
) - connect to SDCARD core
- connect to DDR3
- connect to NVDLA core ( not tested )
- run nvdla driver on Linux ( not implemented )
- run ml projects ( not implemented )
RISCV
core was generated with https://bar.eecs.berkeley.edu/projects/rocket_chip.html
and was configured for RochetChip
version with virtual memory , i$ and d$.
Github project for RocketChip
: https://github.com/chipsalliance/rocket-chip/blob/master/README.md
Github project for NVDLA
: https://github.com/nvdla
gen_linux_img
- steps to build Linux for RocketChipimg
- diagramsip-cores
- ip cores teste with RocketChipnvdla
- rtl for NVIDIA Deep Learning Accelerator (NOT
connected to RocketChip )qmtech_board
- Vivado board configurationvivado_proj
- RocketChip project ( constraints & ip cores )
board
Qmtech Wukong :fpga
- XILINX XC7A100T ( 101,440 LC )ddr3
- MICRON MT41K128M16JT-125:K, 256Mspi
- S25FL128L,16Meth
- RealTek RTL8211EGclk
- 50 MHz
EDA
- Vivado/Vitis
axi4-uart
- AXI4 UARTsdc
- AXI4 SDC controllerddr3
- AXI4 Xilinx MIG / from Github project DDR
- README in folder
gen_linux_img
- Follow steps from github project fpga-rocket-chip
- Append content of
DTS
file ( vivado_proj/bootrom.dts ) from step 1.3 Preparing the project
-
Add wukong target to Vivado
-
Project contains following components :
- RocketChip cpu
- DDR controller
- IO : SPI & SDC & UART
- PLL
- BSCAN
-
Generate project
- cd /vivado_proj
- vivado -mode batch -source riscv-ml.tcl
-
Check memory address :
IP core | ADDRESS |
---|---|
RocketChip/DMA | 0x0000_0000 |
IO/SPI | 0x44A0_0000 |
IO/UART | 0x6001_0000 |
IO/SDC | 0x6000_0000 |
DDR/mig_7 | 0x8000_0000 - 0xFFFF_FFFF |
- Check folder
gen_linux_img
to build Linux and create sdcard - Boot log :
- Project is NOT tested or connected to RocketChip
- linux driver - https://github.com/caihuoq/nvdla
- rtl - folder
nvdla