Mips-pipeline-CPU

A 5-stage pipeline CPU that supports 50 MIPS instructions with Verilog.

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
ALU.v		ALU.v
CP0.v		CP0.v
DM.v		DM.v
DREG.v		DREG.v
DataEXT.v		DataEXT.v
EREG.v		EREG.v
EXT.v		EXT.v
FORWARDctrl.v		FORWARDctrl.v
IM.v		IM.v
MREG.v		MREG.v
MUX.v		MUX.v
Mult.v		Mult.v
NPC.v		NPC.v
PAUSEctrl.v		PAUSEctrl.v
PC.v		PC.v
PCADD.v		PCADD.v
README.md		README.md
RF.v		RF.v
Timer_debug.v		Timer_debug.v
WREG.v		WREG.v
bridge.v		bridge.v
ctrl.v		ctrl.v
microsystem.v		microsystem.v
mips.v		mips.v
mipspipeline.png		mipspipeline.png
timer0.v		timer0.v
timer1.v		timer1.v
timerfinal.v		timerfinal.v

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