学习安全运营的记录 | The knowledge base of security operation
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Updated
Aug 27, 2023 - HTML
学习安全运营的记录 | The knowledge base of security operation
Awesome list of keywords and artifacts for Threat Hunting sessions
Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals
Quickly pin sources, launch multiple investigations, and copy your references - All in 1-click!
SOC simulation system Uses Rsync file, Message Queue (Kafka...) mechanism to send to the Log receiving system. The Log receiving system includes Elastic Search and GrayLog for processing.
This repository is a group-project related to the class: IDG1293 - Avansert CSS
Pipelining and timing issues in CPU data-paths. Principles of RISC-type CPU instruction set and architecture. Structural, data and control hazards in a RISC processor, forwarding loops, branch mechanisms. Memory architectures in CPUs such as register files and caches. UART, I2C protocols.
SideLine is a software-based power side-channel analysis vector. It uses delay-lines (located in SoC memory controllers) as power meters.
Repository for our 2022 SOC Healthy NYC data requests
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