- Berkeley, California
- https://people.eecs.berkeley.edu/~tianruiwei/
- in/tianruiwei
- @tianruiwei
- @tianruiwei@discuss.systems
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openpiton Public
Forked from PrincetonUniversity/openpitonThe OpenPiton Platform
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VossII Public
Forked from TeamVoss/VossIIThe source code to the Voss II Hardware Verification Suite
Verilog Apache License 2.0 UpdatedJul 9, 2024 -
riscv-boom Public
Forked from riscv-boom/riscv-boomSonicBOOM: The Berkeley Out-of-Order Machine
Scala BSD 3-Clause "New" or "Revised" License UpdatedJul 2, 2023 -
yosys Public
Forked from YosysHQ/yosysYosys Open SYnthesis Suite
C++ ISC License UpdatedJun 28, 2023 -
firesim Public
Forked from firesim/firesimFireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud
Scala Other UpdatedJun 17, 2023 -
chipyard Public
Forked from ucb-bar/chipyardAn Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
C BSD 3-Clause "New" or "Revised" License UpdatedJun 12, 2023 -
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bitwise Public
Forked from mellowcandle/bitwiseTerminal based bit manipulator in ncurses
C GNU General Public License v3.0 UpdatedMay 10, 2023 -
riscv-isa-sim Public
Forked from riscv-software-src/riscv-isa-simSpike, a RISC-V ISA Simulator
C Other UpdatedApr 26, 2023 -
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testchipip Public
Forked from ucb-bar/testchipipScala BSD 3-Clause "New" or "Revised" License UpdatedApr 9, 2023 -
FLORA Public
Forked from biruk-belay/FLORAA partial reconfiguration floorplanner for Xilinx FPGAs.
C++ UpdatedMar 14, 2023 -
FireMarshal Public
Forked from firesim/FireMarshalSoftware workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
Python Other UpdatedMar 2, 2023 -
OmnixtendEndpoint Public
Forked from chipsalliance/OmnixtendEndpointHardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.
Bluespec Apache License 2.0 UpdatedFeb 3, 2023 -
verilog-ext Public
Forked from gmlarumbe/verilog-extVerilog Extensions for Emacs
Emacs Lisp GNU General Public License v3.0 UpdatedJan 24, 2023 -
chisel3 Public
Forked from chipsalliance/chiselChisel 3: A Modern Hardware Design Language
Scala Apache License 2.0 UpdatedJan 18, 2023 -
rocket-chip Public
Forked from chipsalliance/rocket-chipRocket Chip Generator
Scala Other UpdatedJan 5, 2023 -
rocket-chip-blocks Public
Forked from chipsalliance/rocket-chip-blocksRTL blocks compatible with the Rocket Chip Generator
Scala Apache License 2.0 UpdatedDec 31, 2022 -
cocotb Public
Forked from cocotb/cocotbcocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Python BSD 3-Clause "New" or "Revised" License UpdatedDec 28, 2022 -
junest Public
Forked from fsquillace/junestThe lightweight Arch Linux based distro that runs, without root privileges, upon any Linux distro
Shell GNU General Public License v3.0 UpdatedNov 27, 2022 -
cpython Public
Forked from python/cpythonThe Python programming language
Python Other UpdatedNov 8, 2022 -
cocotb-test Public
Forked from themperek/cocotb-testUnit testing for cocotb
Python BSD 2-Clause "Simplified" License UpdatedNov 8, 2022 -
staged-recipes Public
Forked from conda-forge/staged-recipesA place to submit conda recipes before they become fully fledged conda-forge feedstocks
Python BSD 3-Clause "New" or "Revised" License UpdatedNov 8, 2022 -
cva6 Public
Forked from openhwgroup/cva6The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
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corescore Public
Forked from olofk/corescoreCoreScore
Verilog Apache License 2.0 UpdatedJun 24, 2022 -
ariane-sdk Public
Forked from openhwgroup/cva6-sdkAriane SDK containing RISC-V tools and Buildroot
Makefile UpdatedJun 21, 2022 -
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microwatt Public
Forked from antonblanchard/microwattA tiny Open POWER ISA softcore written in VHDL 2008
Verilog Other UpdatedMar 1, 2022 -
dma_ip_drivers Public
Forked from Xilinx/dma_ip_driversXilinx QDMA IP Drivers
C UpdatedJan 20, 2022