Cache structure

[mahdi259]

Hi
I have a question about block size of caches. According to datasheet, cache is direct mapped. So how a block size of greater than 4 is handled? Does it work like a 2-way set associative cache in 8 bytes for block size?
Thanks

[stnolting]

Imagine a cache configuration with 4 blocks with a block size of 16 bytes. Fur such a cache configuration, each address (applied to the cache) is decomposed into 3 parts: a tag ("TAG"), a block number ("B") and a block offset ("offs"):

 31                 6 5 4 3  0 
+--------------------+---+----+
|         TAG        | B |offs|
+--------------------+---+----+

• There are 4 bits for the block offset since each block has a size of 2^4=16 bytes.
• Two bits are used to identify the actual bit block since we have 2^2=4 blocks in total.
• The remaining 32-2-4=26 bits are used for the tag that identifies one specific block.

This layout implies that each block is 16-byte aligned. For example, accessing address 0x10000027 will index the 16-byte memory chunk starting at address 0x10000020 (lowest 4 bits are cleared as the block is aligned to a 16-byte boundary).

Inside the cache, block 2 is used (since bits [6:5] [5:4] of the address = 0b10). This block can only take data from one specific memory chunk that has the address "TAG & block number" - that makes the cache direct-mapped.

If you increase the block size, the "B" section of the decomposed address just gets wider (while the TAG section shrinks).

Does that answer your question? Because I don't know exactly what you're getting at 😅

[mahdi259]

Thanks for your comprehensive explanation. I had misunderstood direct mapped concept while using block sizes greater than 4.

Two bits are used to identify the actual bit since we have 2^2=4 blocks in total.

You mean actual Block, right?

Inside the cache, block 2 is used (since bits [6:5] of the address = 0b10). This block can only take data from one specific memory chunk that has the address "TAG & block number" - that makes the cache direct-mapped.

You mean bits [5:4] of address, right?

This layout implies that each block is 16-byte aligned. For example, accessing address 0x10000027 will index the 16-byte memory chunk starting at address 0x10000020 (lowest 4 bits are cleared as the block is aligned to a 16-byte boundary).

So with one cache miss, the cache will be loaded with 4 memory words and the next e.g. instructions or data accesses will benefit cached data and experience fewer delay, right?

[stnolting]

You mean actual Block, right?
You mean bits [5:4] of address, right?

Right. Sorry, typos... 🙈 I'll fix them in the original post.

So with one cache miss, the cache will be loaded with 4 memory words and the next e.g. instructions or data accesses will benefit cached data and experience fewer delay, right?

That's right. Caches utilize the program's temporal and spatial localities.

• temporal locality: It is very likely that a data word that has already been referenced will be referenced again in the future.
• spatial locality: It is very likely that a neighboring data word of an already referenced data word will also be referenced in the future.

[mahdi259]

Thanks a lot