Writting on IDEM directly from HW layer

[SergioNDuarte]

Hello,

I need to ask for your help. I’m currently using the neorv32 on a DE0 nano for a project. I need to scope a bus and detect a specific message with the hardware layer and when detected, store the data on the RAM so I can access it with the software layer.

My problem is that I can't write on the RAM from the hardware layer. I kept the same configuration (@X8000 0000 for the idmem) but I can’t figure out how to write on a specific adress of the idmem directly from the hardware layer. I tried to change the idmem process in a way so I can trigger a write command to a specific address but it didn’t work well. I also tried to use the IP’s but again, i’m not sure if it is possible to have a direct access to the idmem from the hardware layer (I saw on the documentation that the internal memories could not be accessed directly but is it the case if I use the avalon bus to access the memory?). Other thing : I spotted on the documentation and in a forum that I should use an external memory and use the wishbone protocol to write on the memory but is it really necessary? Do I have any other option to do it without using an external memory?

I think that the best and easiest way would be to use the IP’s and the avalon bus from the Git repertory but I think I'm missing a step or two to combine them all.

[stnolting]

Hey there!

I am not really sure what you are trying to implement. Do you need direct low-level memory access to arbitrary addresses from the software running on the processor or do you want to access the DMEM from another hardware module (something like a DMA concept)?

[SergioNDuarte]

Thanks for your quick answer.

For my case it would be to access the DMEM from another hardware module. A simple example to illustrate what I'm trying to achieve would be to launch the Boot-loader, load a binary compiled .C file with a program that will periodically(Ex: each 1sec) show/print on a console the value of a specific address at the DMEM range. Meanwhile, if a press a physical switch (to simulate the detection of a signal), i would like to write a value at that specific address (updating the content at this specific address needs to be done only by the HW layer). At the end, the endless loop made on the Soft layer should allow me to see the value at that specific address change for each time I trigger the signal on the HW layer.

[stnolting]

Ok I think I understood what you are trying to do 😉

Only the CPU core can access the processor-internal IMEM and DMEM. If you want to access those memories also from other "cores" you need to use processor-external memories for that. But I think for your application a tiny multi-ported RAM connected to the external bus interface (so the CPU can access it) and also connected to your "signal capture logic" should be sufficient.

There are predefined functions to read/write bytes, half-words and words from/to any address. For example:

neorv32/sw/lib/include/neorv32_cpu.h

Lines 169 to 185 in d828c7d

	/**********************************************************************//**
	* Load unsigned word from address space.
	*
	* @note An unaligned access address will raise an alignment exception.
	*
	* @param[in] addr Address (32-bit).
	* @return Read data word (32-bit).
	**************************************************************************/
	inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_word(uint32_t addr) {
	register uint32_t reg_addr = addr;
	register uint32_t reg_data;
	asm volatile ("lw %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
	return (uint32_t)reg_data;
	}

[SergioNDuarte]

I'm getting the idea of sharing an external memory between devices but, when you propose to use a tiny multi-ported RAM connected to the external bus interface isn't it the same as to define an external RAM and share it with the Wishbone gateway?

[stnolting]

Right, those are identical. But I would use a dedicated processor-external RAM and not make the DMEM processor-external - this would decrease performance.

[SergioNDuarte]

Ok, I now see the difference between the 2 methods. I think I have all the details I needed for my project. It's much clear now.

Thank you very much for your help.

[agamez]

Hi!

I believe I'm trying to do something similar as Sergio here.

What I want to do is receive data from an ADC and place it somewhere accessible to the CPU, so it can do some signal processing (a couple or FIR filters, for example), and place it back somewhere for the programmable logic to acquire and continue the treatment of this data.

I was thinking that the slink interface would be good for that, but I see that it's been removed. It looks like the idea given here is the most straightforward way to do this, is that right? It'd be like a DMA without a proper DMA controller, just knowing beforehand the read/write addresses of an external block of RAM.

Still, I find that an streaming I/O interface would be better for my processor assisted signal processing! IS there any plan to implement something like that back again? Or maybe I should just use an older version of neorv32, is that a good idea?

Thanks!

[stnolting]

Hey!

The stream link interface has been removed as it appeared to be completely over-engineered. If you attach several FIFOs (like rtl/core/neorv32_fifo.vhd) to the processor's bus interface you'll get the same functionality - but with all the flexibility you actually need. So this is what I recommend here.

Maybe something like the SLINK might be re-added in the future, but right now I am not sure what that would look like. But I'm open for ideas! 😉

[mr-potato-head]

Hi Stephan,
First thing first : your work is just amazing. I'm a beginner in SoC/VHDL etc. and with your awesome doc I could run a neorv32 CPU on a custom Cyclone 4 based board. Many thanks for this !
I'm trying to do exactly the same thing on my board (exchange some data between hardware and software parts). The fifos connected to the bus looks a very good idea. Do you have somewhere an example of custom device connected to the bus ? or fifo usage example ?
Thanks for your help 🚀

[stnolting]

Hey @mr-potato-head.

First thing first : your work is just amazing.

Thank you very much for the nice words! :)

I'm a beginner in SoC/VHDL etc. and with your awesome doc I could run a neorv32 CPU on a custom Cyclone 4 based board. Many thanks for this !

That's really great! 🚀

I'm trying to do exactly the same thing on my board (exchange some data between hardware and software parts).

So you have a hardware module generating data that shall be written to the processor's memory?

Could you give some more details?

The fifos connected to the bus looks a very good idea. Do you have somewhere an example of custom device connected to the bus ? or fifo usage example ?

The stream link interface (SLINK) has been added back to the core. You could use the RX link to send data that gets buffered in the SLINK-internal FIFO. The CPU could then check periodically (or triggered via the SLINK interrupt) whether data is available. Alternatively, you could also use the DMA to automatically write data from the SLINK FIFO to the memory without any CPU interaction at all.

[mr-potato-head]

@stnolting thank you for your answer.

So you have a hardware module generating data that shall be written to the processor's memory?
Could you give some more details?

Sure, it is just some data coming from USB through an FTDI FT2232. I need to provide the data to the CPU.
For now the data are placed in a FPGA fifo and I use the GPIO directly to read/write with some kind of bit-banging stuff 🤮
So, I just want to really benefit of the neorv32 peripherals to do something cleaner and more efficient.

The stream link interface (SLINK) has been added back to the core. You could use the RX link to send data that gets buffered in the SLINK-internal FIFO. The CPU could then check periodically (or triggered via the SLINK interrupt) whether data is available. Alternatively, you could also use the DMA to automatically write data from the SLINK FIFO to the memory without any CPU interaction at all.

Nice, I'm going to have a look on the SLink feature right now, Thank you for pointing this out to me. Yesterday, I was able to read my FPGA fifos and give the data to the CPU using the XBUS thank to this example (https://github.com/emb4fun/neorv32-examples/tree/master/de0-nano/de0n-neorv32-sdram-direct). It helped me understand how the bus works. It's really cool and "transparent" for the CPU.

Many thanks Stephan !

[stnolting]

For now the data are placed in a FPGA fifo and I use the GPIO directly to read/write with some kind of bit-banging stuff

That's also a nice idea! However, the latency would be rather large with this concept.

Nice, I'm going to have a look on the SLink feature right now [...]

I think the SLINK module should be the right starting point for your application. Feel free to ask if something is unclear.