periphery: bus api update #17
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terpstra
approved these changes
Feb 23, 2018
| require(nMemoryChannels == 1, "Coreplex must have 1 master memory port") | ||
| xilinxvc707mig.node := memBuses.head.toDRAMController | ||
| require(nMemoryChannels == 1, "Core complex must have at most 1 master memory port") | ||
| xilinxvc707mig.node := memBuses.head.toDRAMController(Some("xilinxvc707mig"))() |
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I think the original requirement was more correct.
| private val name = Some("xilinxvc707pcie") | ||
| sbus.fromMaster(name) { xilinxvc707pcie.crossTLOut } := xilinxvc707pcie.master | ||
| xilinxvc707pcie.slave := sbus.toFixedWidthSlave(name) { xilinxvc707pcie.crossTLIn } | ||
| xilinxvc707pcie.control := sbus.toFixedWidthSlave(name) { xilinxvc707pcie.crossTLIn } |
ckdur
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Jan 24, 2024
Bump to latest rocketchip
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