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1. ibex ibex Public

   Forked from lowRISC/ibex

   Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

   SystemVerilog

2. ibex_super_system ibex_super_system Public

   Forked from GregAC/ibex_super_system

   Ibex super system example with UART included

   SystemVerilog

3. blinky blinky Public

   Forked from fusesoc/blinky

   Example LED blinking project for your FPGA dev board of choice

   Tcl

4. edalize edalize Public

   Forked from olofk/edalize

   An abstraction library for interfacing EDA tools

   Python

5. verilator verilator Public

   Forked from verilator/verilator

   Verilator open-source SystemVerilog simulator and lint system

   C++

6. opentitan opentitan Public

   Forked from lowRISC/opentitan

   OpenTitan: Open source silicon root of trust

   SystemVerilog