Your entire server infrastructure at your fingertips

lightweight, command line SMTP email client

The CSV magician

Lightning-fast and Powerful Code Editor written in Rust

♏ 一款浏览器端的 Markdown 编辑器，支持所见即所得（富文本）、即时渲染（类似 Typora）和分屏预览模式。An In-browser Markdown editor, support WYSIWYG (Rich Text), Instant Rendering (Typora-like) and Split View modes.

Render markdown on the CLI, with pizzazz! 💅🏻

Vim-mode Extension For Yank-Note

A highly extensible Markdown editor. Version control, AI Copilot, mind map, documents encryption, code snippet running, integrated terminal, chart embedding, HTML applets, Reveal.js, plug-in, and m…

XTulator is a portable, open source x86 PC emulator currently supporting the 8086 instruction set and 80186 extensions.

8086, i386, ARMv7, Z80, 6502, CHIP-8

Simple x86 and DOS emulator for the Linux terminal.

Official repository for 8086tiny: a tiny PC emulator/virtual machine

Intel IA16 emulator for embedded development

A simple wrapper around make to colorize the output.

Protected Low-overhead Object Oriented Programming with ANSI-C

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

An IBM PC/XT emulator written in Rust.

A Hardware-Generated JSON CPU Test Suite for the Intel 8088

A language-agnostic JSON-encoded instruction-by-instruction test suite for the 8088, 68000, 65816, 65[c]02 and SPC700 that includes bus activity.

An Arduino interface for 8088 CPUs.

Collection of C++ classes to create Verilator Testbenches

Basic VCD comparison tool, for Verilator testing

SystemVerilog implemention of QEMU PCI edu device

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Notes on Verilator

SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions

Facilitates building open source tools for working with hardware description languages (HDLs)

Adding UVM support to Icarus Verilog (and Verilator in near future) by taking a step-by-step, bottom-up approach.

RISCV model for Verilator/FPGA targets

Python wrapper for verilator model