Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

An MLIR-based toolchain for AMD AI Engine-enabled devices.

This package includes the implementation for Sparse-Triangular-Solve (SpTRSV) for Single-node Multi-GPU (scale-up) platforms such as NVIDIA DGX-1 and DGX-2. It is duplicated from https://github.com…

An auto-tuning framework to accelerate Sparse Triangular Solve on GPU

[FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver

Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators

CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture

Examples utilizing cuSolver and cuSolverMg

A sample code for sparse cholesky solver with cuSPARSE and cuSOLVER library

Systolic array implementations for Cholesky, LU, and QR decomposition

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