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That's strange. I just updated SweRVolf to use SweRV 1.5 and didn't see any issues with Vivado. Doing standalone Vivado synthesis (e.g. with fusesoc run --target=synth chipsalliance.org:cores:SweRV_EH1 --part=xc7a100tcsg324-1) also works fine
The Vivado synthetizer does not like the ' in
rden <= '0;
wren <= '0;
I don't know anything about Verilog.
The following fixes the syntax issues but I'm unsure whether this actually works :
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