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Commits on Mar 12, 2021

• reverting to 0242c9e for swerv_config_gen.py

  

  Ajay Nath

  authored and

  Ajay Nath

  committedMar 12, 2021
  81bff1c

Commits on Feb 19, 2021

• Merge pull request chipsalliance#93 from antmicro/variable-order-fix

  aprnath

  committedFeb 19, 2021
  d4e7b25

Commits on Feb 17, 2021

• Do not use variables before declaration

  tgorochowik

  committedFeb 17, 2021
  74a6bdb

Commits on Feb 16, 2021

• Delete testbench/tests/cmark_dccm directory

  aprnath

  committedFeb 16, 2021
  f3da044

Commits on Feb 3, 2021

• Update README.md

  tmw-wdc

  committedFeb 3, 2021
  5e23462

• Removed dead code.

  

  Joseph Rahmeh

  committedFeb 3, 2021
  695883a

• Version 1.9

  

  Joseph Rahmeh

  committedFeb 3, 2021
  0c92ea1

Commits on Jan 27, 2021

• Version 1.9.

  

  Joseph Rahmeh

  committedJan 27, 2021
  ec254f5

Commits on Jan 21, 2021

• Merge pull request chipsalliance#82 from chipsalliance/quartus_core_fix

  aprnath

  committedJan 21, 2021
  bcb5b33

• Merge pull request chipsalliance#89 from olofk/scan_mode

  aprnath

  committedJan 21, 2021
  bb9f9ef

Commits on Jan 18, 2021

• Remove unused scan_mode input from dmi_wrapper

  olofk

  committedJan 18, 2021
  bcf5057

Commits on Nov 24, 2020

• Only load Vivado TCL files when using Vivado

  olofk

  committedNov 24, 2020
  3918a8d

Commits on Sep 24, 2020

• Merge pull request chipsalliance#76 from olofk/snapshot_dir2

  aprnath

  committedSep 24, 2020
  7332edc

• Explicitly use python3

  olofk

  committedSep 24, 2020
  0242c9e

• Set snapshot dir to a known location in FuseSoC SweRV config generator

  olofk

  committedSep 24, 2020
  801d0f6

Commits on Sep 22, 2020

• Merge pull request chipsalliance#75 from olofk/snapshot_dir

  aprnath

  committedSep 22, 2020
  1e8c6e3

• Adapt FuseSoC SweRV config generator wrt new snapshot dir

  olofk

  committedSep 22, 2020
  2627ccc

• Updated per issue chipsalliance#70

  

  Ajay Nath

  authored and

  Ajay Nath

  committedSep 22, 2020
  f32b634

Commits on Sep 19, 2020

• Update release-notes.md

  tmw-wdc

  committedSep 19, 2020
  3c50837

Commits on Sep 18, 2020

• Updated version in swerv.core

  

  Joseph Rahmeh

  committedSep 18, 2020
  e63dfe1

• Updated branch number in README file.

  

  Joseph Rahmeh

  committedSep 18, 2020
  d6024bc

• Updated branch number in README file.

  

  Joseph Rahmeh

  committedSep 18, 2020
  d395a96

• Added testbench/hex directory.

  

  Joseph Rahmeh

  committedSep 18, 2020
  8caf5f6

• Updated PRM.

  

  Joseph Rahmeh

  committedSep 18, 2020
  95e9589

• New branch: branch1.8

  

  Joseph Rahmeh

  committedSep 18, 2020
  5e61358

Commits on Aug 19, 2020

• Merge pull request chipsalliance#68 from olofk/fusesoc_v1_7

  jrahmeh

  committedAug 19, 2020
  499378d

• Update SweRV version in core description file to 1.7

  olofk

  committedAug 19, 2020
  9e0aeed

Commits on Jun 26, 2020

• Update README.md

  tmw-wdc

  committedJun 26, 2020
  48f01f1

• Upped version.

  

  Joseph Rahmeh

  committedJun 26, 2020
  5f905a0

• Updated PRM.

  

  Joseph Rahmeh

  committedJun 26, 2020
  ae1b1bc

• Branch for version 1.7

  

  Joseph Rahmeh

  committedJun 26, 2020
  8065eef

Commits on May 27, 2020

• Reverted change related to enum assign as it broke some Verilog tools.

  

  Joseph Rahmeh

  committedMay 27, 2020
  0555dd8

• Merge pull request chipsalliance#55 from dawidzim/riviera_fusesoc

  jrahmeh

  committedMay 27, 2020
  5a004dd

• Merge pull request chipsalliance#49 from dawidzim/enum_from_diff_type

  jrahmeh

  committedMay 27, 2020
  27507b7

Commits on May 26, 2020

• update swerv.core for Riviera-PRO

  dawidzim

  committedMay 26, 2020
  23c6ce8

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