Command-line Git information tool

Cutting stock problem optimizer

Tools for running FPGA vendor toolchains with Docker

SystemRDL 2.0 language compiler front-end

Control and status register code generator toolchain

Build your hardware, easily!

An open-source HDL register code generator fast enough to run in real time.

Neofetch configs put into a convinient repository

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

An extremely fast Python linter and code formatter, written in Rust.

A starting point for understanding how to grow vegetables at home

A template for getting started with FPGA core development

An abstraction library for interfacing EDA tools

Tool for generating multi-purpose makefiles for FPGA projects (clone of hdlmake from CERN)

VUnit GitHub action

VHDL synthesis (based on ghdl)

Yosys Open SYnthesis Suite

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

VHDL 2008/93/87 simulator

Package manager and build abstraction tool for FPGA/ASIC development

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

VUnit is a unit testing framework for VHDL/SystemVerilog