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LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled

Verilog 2 1 Updated Jan 3, 2021

Various projects for the Nexys4DDR board from Digilent

VHDL 126 15 Updated Aug 30, 2023

notes while reviewing computer networking by taking online course "the bits and bytes of computer network" on Coursera from Google

12 3 Updated Jun 7, 2020

VHDL library for 10 GbE supporting UDP/IP, ARP, ICMP and DHCP

VHDL 5 Updated Jun 1, 2023

A huge VHDL library for FPGA development

VHDL 323 55 Updated Sep 28, 2024

Greetings! 👋 I'm Loga Aswin, diving into a 100-day data science immersion from Python fundamentals to real-world applications. This space will be a live documentation of my journey, where code meet…

Jupyter Notebook 201 48 Updated Jun 10, 2024

Case study of synchronous FPGA signaling by adjusting the output timing

Tcl 11 2 Updated Aug 16, 2019

Verilog based BCH encoder/decoder

Verilog 107 44 Updated Sep 26, 2022

VHDL src and testbench for LFSR tutorial

VHDL 1 Updated Sep 10, 2022

A PN9 sequence checker for the AD9645 analog-to-digital converter

VHDL 2 2 Updated Feb 27, 2023

Xilinx Embedded Software (embeddedsw) Development

HTML 929 1,062 Updated Jul 26, 2024

Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP

VHDL 35 18 Updated Jun 23, 2021

UART to AXI Stream interface written in VHDL

VHDL 16 4 Updated Oct 20, 2022

Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020

C 50 28 Updated Apr 27, 2017

Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL

VHDL 152 60 Updated Jan 24, 2024

MEGA65 FPGA core

VHDL 240 88 Updated Sep 24, 2024

A software I2C implementation to run on any GPIO pins on any system

C++ 239 33 Updated Aug 23, 2024

Lightweight USB device and host stack for STM32 and other MCUs. Ready for USB 3.0 device.

C 561 175 Updated Nov 30, 2023