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airisc_core_complex Public
Forked from Fraunhofer-IMS/airisc_core_complexFraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals.
Verilog Other UpdatedFeb 25, 2022 -
ara Public
Forked from pulp-platform/araThe PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
C Other UpdatedDec 4, 2022 -
ASAD_DenseNet Public
Forked from xuxiran/ASAD_DenseNetthe implementation of the ASAD_DenseNet
Python MIT License UpdatedApr 21, 2024 -
axi Public
Forked from pulp-platform/axiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SystemVerilog Other UpdatedSep 6, 2022 -
BIThesis Public
Forked from BITNP/BIThesis📖 北京理工大学非官方 LaTeX 模板集合,包含本科、研究生毕业设计模板及更多。🎉 (更多文档请访问 wiki 和 release 中的手册)
TeX LaTeX Project Public License v1.3c UpdatedOct 31, 2022 -
clacc Public
Forked from taoyilee/claccDeep Learning Accelerator (Convolution Neural Networks)
Verilog MIT License UpdatedDec 15, 2017 -
cluster_interconnect Public
Forked from pulp-platform/cluster_interconnectSystemVerilog Other UpdatedFeb 16, 2022 -
CNN-Accelerator-VLSI Public
Forked from lirui-shanghaitech/CNN-Accelerator-VLSIConvolutional accelerator kernel, target ASIC & FPGA
Verilog Apache License 2.0 UpdatedApr 10, 2023 -
CNN-FPGA Public
Forked from QShen3/CNN-FPGA使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用
Verilog MIT License UpdatedJun 18, 2018 -
cocotbext-axi Public
Forked from alexforencich/cocotbext-axiAXI interface modules for Cocotb
Python MIT License UpdatedNov 16, 2023 -
common_cells Public
Forked from pulp-platform/common_cellsCommon SystemVerilog components
SystemVerilog Other UpdatedNov 9, 2022 -
common_verification Public
Forked from pulp-platform/common_verificationSystemVerilog modules and classes commonly used for verification
SystemVerilog Other UpdatedSep 14, 2022 -
convolution_network_on_FPGA Public
Forked from hunterlew/convolution_network_on_FPGACNN acceleration on virtex-7 FPGA with verilog HDL
Verilog UpdatedFeb 27, 2018 -
core-v-mcu Public
Forked from openhwgroup/core-v-mcuThis is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
SystemVerilog Other UpdatedNov 22, 2022 -
core-v-xif Public
Forked from openhwgroup/core-v-xifRISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
UpdatedJul 18, 2022 -
CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2 Public
Forked from karthisugumar/CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Accelerator
SystemVerilog UpdatedDec 14, 2019 -
cv32e40p Public
Forked from openhwgroup/cv32e40pCV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
SystemVerilog Other UpdatedDec 2, 2022 -
cv32e40x Public
Forked from openhwgroup/cv32e40x4 stage, in-order, compute RISC-V core based on the CV32E40P
SystemVerilog Other UpdatedNov 18, 2022 -
cva6 Public
Forked from openhwgroup/cva6The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
SystemVerilog Other UpdatedDec 4, 2022 -
e203_hbirdv2 Public
Forked from riscv-mcu/e203_hbirdv2The Ultra-Low Power RISC-V Core
Verilog Apache License 2.0 UpdatedFeb 24, 2022 -
ECE-564-Convolutional-Neural-Network-Accelerator Public
Forked from Di5h3z/ECE-564-Convolutional-Neural-Network-AcceleratorA Verilog implementation of a CNN accelerator.
Verilog UpdatedNov 19, 2021 -
EigenVector Public
Forked from moshe-olshansky/EigenVectorPOSSUMM - PCA of Sparse, SUper Massive Matrices
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ES203-COA-CNN Public
Forked from anupam-io/ES203-COA-CNNES-203 Computer Organization & Architecture CNN on FPGA board
Verilog UpdatedFeb 23, 2022 -
External-Attention-tensorflow Public
Forked from ccfco/External-Attention-tensorflow🍀 Tensorflow implementation of various Attention Mechanisms, MLP, Re-parameter, Convolution, which is helpful to further understand papers.⭐⭐⭐
Python UpdatedFeb 1, 2023 -
EyerissF Public
Forked from jneless/EyerissFAn Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"
Python GNU Lesser General Public License v2.1 UpdatedDec 22, 2020 -
face_recognize Public
Forked from David-Guo/face_recognizeMatlab PCA 人脸识别
MATLAB UpdatedJun 25, 2015 -
FFT Public
Forked from nelsoncsc/FFTHardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm
SystemVerilog UpdatedMar 3, 2018 -
FFT_R2SDF Public
Forked from chpapantonis/FFT_R2SDFRadix 2 DIT FFT Single Path Delay Feedback
VHDL UpdatedApr 17, 2015 -
FPGA-CNN Public
Forked from diaoenmao/FPGA-CNNFPGA implementation of Cellular Neural Network (CNN)
Verilog MIT License UpdatedMar 30, 2018 -
FPGA-DDR-SDRAM Public
Forked from WangXuan95/FPGA-DDR-SDRAMAn AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。
Verilog UpdatedJun 9, 2023