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Fix: Update HE Cache bias command line input #3029

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merged 6 commits into from
Oct 18, 2023
Merged

Fix: Update HE Cache bias command line input #3029

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875cfbb
Fix: Update HE Cache bias command line input
anandaravuri Oct 16, 2023
1ed549e
Merge branch 'master' into aravuri/fix_cxl_cache_cmd_1
anandaravuri Oct 17, 2023
c2c5488
fix: he-cache stride typo
anandaravuri Oct 17, 2023
dcaa725
Fix: set stride to 3 for target fpga memory
anandaravuri Oct 17, 2023
2c04125
fix: change he-cache output message
anandaravuri Oct 17, 2023
d170f5a
Merge branch 'master' into aravuri/fix_cxl_cache_cmd_1
anandaravuri Oct 17, 2023
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127 changes: 80 additions & 47 deletions samples/cxl_host_exerciser/cxl_he_cache_cmd.h
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,8 @@ class he_cache_cmd : public he_cmd {
public:
he_cache_cmd()
: he_continuousmode_(false), he_contmodetime_(0), he_linerep_count_(0),
he_stide_(0), he_test_(0), he_test_all_(false), he_dev_instance_(0) {}
he_stride_(0), he_test_(0), he_test_all_(false), he_dev_instance_(0),
he_stride_cmd_(false) {}

virtual ~he_cache_cmd() {}

Expand Down Expand Up @@ -94,9 +95,9 @@ class he_cache_cmd : public he_cmd {
->default_val("host");

app->add_option("--bias", he_bias_,
"host exerciser run on hostmem or fpgamem")
"CXL IP memory access Bias mode: host or device")
->transform(CLI::CheckedTransformer(he_bias))
->default_val("hostmem");
->default_val("host");

// device cache0 or cache1
app->add_option("--device", he_dev_instance_,
Expand All @@ -106,7 +107,7 @@ class he_cache_cmd : public he_cmd {
->default_val("/dev/dfl-cxl-cache.0");

// Set sride
app->add_option("--stride", he_stide_, "Set stride value")
app->add_option("--stride", he_stride_, "Set stride value")
->transform(CLI::Range(0, 3))->default_val("0");

// Line repeat count
Expand Down Expand Up @@ -138,9 +139,6 @@ class he_cache_cmd : public he_cmd {
he_info_.value = host_exe_->read64(HE_INFO);
host_exe_->write64(HE_RD_NUM_LINES, FPGA_512CACHE_LINES);

// Set Stride to 3 for FPGA read/write cache hit/miss
he_stide_ = 3;

cout << "Read number Lines:" << FPGA_512CACHE_LINES << endl;
cout << "Line Repeat Count:" << he_linerep_count_ << endl;
cout << "Read address table size:" << he_info_.read_addr_table_size << endl;
Expand All @@ -155,9 +153,16 @@ class he_cache_cmd : public he_cmd {

// set RD_ADDR_TABLE_CTRL
rd_table_ctl_.value = 0;
if (he_stide_ > 0) {
if (he_stride_cmd_) {
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = he_stride_;
} else if (he_target_ == HE_TARGET_FPGA) {
// Set Stride to 3 for Target FPGA Memory
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = 3;
} else {
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = he_stide_;
rd_table_ctl_.stride = he_stride_;
}
host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value);

Expand All @@ -178,7 +183,7 @@ class he_cache_cmd : public he_cmd {
he_start_test();

// wait for completion
if (!he_wait_test_completion()) {
if (!he_wait_test_completion(HE_PRTEST_SCENARIO)) {
he_perf_counters();
host_exerciser_errors();
host_exe_->free_cache_read();
Expand All @@ -200,9 +205,16 @@ class he_cache_cmd : public he_cmd {

// set RD_ADDR_TABLE_CTRL
rd_table_ctl_.value = 0;
if (he_stide_ > 0) {
if (he_stride_cmd_) {
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = he_stride_;
} else if (he_target_ == HE_TARGET_FPGA) {
// Set Stride to 3 for Target FPGA Memory
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = he_stide_;
rd_table_ctl_.stride = 3;
} else {
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = he_stride_;
}
host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value);

Expand Down Expand Up @@ -248,9 +260,6 @@ class he_cache_cmd : public he_cmd {
he_info_.value = host_exe_->read64(HE_INFO);
host_exe_->write64(HE_RD_NUM_LINES, FPGA_512CACHE_LINES);

// Set Stride to 3 for FPGA read/write cache hit/miss
he_stide_ = 3;

cout << "Read/write number Lines:" << FPGA_512CACHE_LINES << endl;
cout << "Line Repeat Count:" << he_linerep_count_ << endl;
cout << "Read address table size:" << he_info_.read_addr_table_size << endl;
Expand All @@ -266,9 +275,16 @@ class he_cache_cmd : public he_cmd {

// set RD_ADDR_TABLE_CTRL
rd_table_ctl_.value = 0;
if (he_stide_ > 0) {
if (he_stride_cmd_) {
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = he_stide_;
rd_table_ctl_.stride = he_stride_;
} else if (he_target_ == HE_TARGET_FPGA) {
// Set Stride to 3 for Target FPGA Memory
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = 3;
} else {
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = he_stride_;
}
host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value);

Expand All @@ -289,7 +305,7 @@ class he_cache_cmd : public he_cmd {
he_start_test();

// wait for completion
if (!he_wait_test_completion()) {
if (!he_wait_test_completion(HE_PRTEST_SCENARIO)) {
he_perf_counters();
host_exerciser_errors();
host_exe_->free_cache_read_write();
Expand Down Expand Up @@ -317,9 +333,16 @@ class he_cache_cmd : public he_cmd {

// Set WR_ADDR_TABLE_CTRL
wr_table_ctl_.value = 0;
if (he_stide_ > 0) {
if (he_stride_cmd_) {
wr_table_ctl_.enable_address_stride = 1;
wr_table_ctl_.stride = he_stride_;
} else if (he_target_ == HE_TARGET_FPGA) {
// Set Stride to 3 for Target FPGA Memory
wr_table_ctl_.enable_address_stride = 1;
wr_table_ctl_.stride = he_stide_;
wr_table_ctl_.stride = 3;
} else {
wr_table_ctl_.enable_address_stride = 1;
wr_table_ctl_.stride = he_stride_;
}
host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, wr_table_ctl_.value);
host_exe_->write64(HE_WR_NUM_LINES, FPGA_512CACHE_LINES);
Expand Down Expand Up @@ -364,9 +387,6 @@ class he_cache_cmd : public he_cmd {
he_info_.value = host_exe_->read64(HE_INFO);
host_exe_->write64(HE_RD_NUM_LINES, FPGA_512CACHE_LINES);

// Set Stride to 3 for FPGA read/write cache hit/miss
he_stide_ = 3;

cout << "Read number Lines:" << FPGA_512CACHE_LINES << endl;
cout << "Line Repeat Count:" << he_linerep_count_ << endl;
cout << "Read address table size:" << he_info_.read_addr_table_size << endl;
Expand All @@ -380,9 +400,16 @@ class he_cache_cmd : public he_cmd {

// set RD_ADDR_TABLE_CTRL
rd_table_ctl_.value = 0;
if (he_stide_ > 0) {
if (he_stride_cmd_) {
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = he_stride_;
} else if (he_target_ == HE_TARGET_FPGA) {
// Set Stride to 3 for Target FPGA Memory
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = 3;
} else {
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = he_stide_;
rd_table_ctl_.stride = he_stride_;
}
host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value);

Expand Down Expand Up @@ -437,9 +464,6 @@ class he_cache_cmd : public he_cmd {
he_info_.value = host_exe_->read64(HE_INFO);
host_exe_->write64(HE_WR_NUM_LINES, FPGA_512CACHE_LINES);

// Set Stride to 3 for FPGA read/write cache hit/miss
he_stide_ = 0x3;

cout << "Read/write number Lines:" << FPGA_512CACHE_LINES << endl;
cout << "Line Repeat Count:" << he_linerep_count_ << endl;
cout << "Read address table size:" << he_info_.read_addr_table_size << endl;
Expand All @@ -455,9 +479,16 @@ class he_cache_cmd : public he_cmd {

// Set WR_ADDR_TABLE_CTRL
wr_table_ctl_.value = 0;
if (he_stide_ > 0) {
if (he_stride_cmd_) {
wr_table_ctl_.enable_address_stride = 1;
wr_table_ctl_.stride = he_stride_;
} else if (he_target_ == HE_TARGET_FPGA) {
// Set Stride to 3 for Target FPGA Memory
wr_table_ctl_.enable_address_stride = 1;
wr_table_ctl_.stride = he_stide_;
wr_table_ctl_.stride = 3;
} else {
wr_table_ctl_.enable_address_stride = 1;
wr_table_ctl_.stride = he_stride_;
}
host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, wr_table_ctl_.value);

Expand Down Expand Up @@ -527,10 +558,8 @@ class he_cache_cmd : public he_cmd {

// set RD_ADDR_TABLE_CTRL
rd_table_ctl_.value = 0;
if (he_stide_ > 0) {
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = he_stide_;
}
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = he_stride_;
host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value);

// Allocate DSM buffer
Expand Down Expand Up @@ -611,10 +640,8 @@ class he_cache_cmd : public he_cmd {

// set RD_ADDR_TABLE_CTRL
wr_table_ctl_.value = 0;
if (he_stide_ > 0) {
wr_table_ctl_.enable_address_stride = 1;
wr_table_ctl_.stride = he_stide_;
}
wr_table_ctl_.enable_address_stride = 1;
wr_table_ctl_.stride = he_stride_;
host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, wr_table_ctl_.value);

// Allocate DSM buffer
Expand Down Expand Up @@ -692,10 +719,8 @@ class he_cache_cmd : public he_cmd {

// set RD_ADDR_TABLE_CTR
rd_table_ctl_.value = 0;
if (he_stide_ > 0) {
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = he_stide_;
}
rd_table_ctl_.enable_address_stride = 1;
rd_table_ctl_.stride = he_stride_;
host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value);

// Allocate DSM buffer
Expand Down Expand Up @@ -765,10 +790,8 @@ class he_cache_cmd : public he_cmd {

// set RD_ADDR_TABLE_CTR
wr_table_ctl_.value = 0;
if (he_stide_ > 0) {
wr_table_ctl_.enable_address_stride = 1;
wr_table_ctl_.stride = he_stide_;
}
wr_table_ctl_.enable_address_stride = 1;
wr_table_ctl_.stride = he_stride_;
host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, rd_table_ctl_.value);

// Allocate DSM buffer
Expand Down Expand Up @@ -818,6 +841,11 @@ class he_cache_cmd : public he_cmd {
cout << "numa nodes are available set numa node to 0" << endl;
};

CLI::Option* opt = app->get_option_no_throw("--stride");
if (opt && opt->count() == 1) {
he_stride_cmd_ = true;
}

// reset HE cache
he_ctl_.value = 0;
he_ctl_.ResetL = 0;
Expand All @@ -828,6 +856,10 @@ class he_cache_cmd : public he_cmd {

print_csr();

if (!he_set_bias_mode()) {
return -1;
}

if (he_test_all_ == true) {
int retvalue = 0;
ret = he_run_fpga_rd_cache_hit_test();
Expand Down Expand Up @@ -915,10 +947,11 @@ class he_cache_cmd : public he_cmd {
bool he_continuousmode_;
uint32_t he_contmodetime_;
uint32_t he_linerep_count_;
uint32_t he_stide_;
uint32_t he_stride_;
uint32_t he_test_;
bool he_test_all_;
uint32_t he_dev_instance_;
bool he_stride_cmd_;
};

void he_cache_thread(uint8_t *buf_ptr, uint64_t len) {
Expand Down
55 changes: 33 additions & 22 deletions samples/cxl_host_exerciser/cxl_he_cmd.h
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Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,9 @@
#include "cxl_host_exerciser.h"
#include "he_cache_test.h"

#define HE_TEST_STARTED "Test started ......"
#define HE_PRTEST_SCENARIO "Pretest scenario started ......"

namespace host_exerciser {

class he_cmd : public test_command {
Expand Down Expand Up @@ -223,11 +226,11 @@ class he_cmd : public test_command {
return 0;
}

bool he_wait_test_completion() {
bool he_wait_test_completion(const char* str = HE_TEST_STARTED) {
/* Wait for test completion */
uint32_t timeout = HELPBK_TEST_TIMEOUT;

cout << "Test started ......" << endl;
cout << str << endl;
volatile uint8_t *status_ptr = host_exe_->get_dsm();
while (0 == ((*status_ptr) & 0x1)) {
usleep(HELPBK_TEST_SLEEP_INVL);
Expand All @@ -239,29 +242,37 @@ class he_cmd : public test_command {
return true;
}

void he_start_test() {
// start test
bool he_set_bias_mode() {

switch (he_bias_) {
case HOSTMEM_BIAS:
he_ctl_.bias_support = 0x0;
break;
// Target memory HOST set BIAS host
if (he_target_ == HE_TARGET_HOST) {
he_ctl_.bias_support = HOSTMEM_BIAS;
// Target memory FPGA set BIAS host/device
if (he_bias_ == HOSTMEM_BIAS) {
he_ctl_.bias_support = HOSTMEM_BIAS;
} else {
cerr << "Wrong BIAS mode for specified target memory type" << endl;
return false;
}
} else {
// Target memory FPGA set BIAS host/device
if (he_bias_ == HOSTMEM_BIAS) {
he_ctl_.bias_support = FPGAMEM_HOST_BIAS;
} else {
he_ctl_.bias_support = FPGAMEM_DEVICE_BIAS;
}
}

case FPGAMEM_HOST_BIAS:
he_ctl_.bias_support = 0x2;
break;
return true;
}

case FPGAMEM_DEVICE_BIAS:
he_ctl_.bias_support = 0x3;
break;
default:
he_ctl_.bias_support = 0x0;
}

he_ctl_.Start = 0;
host_exe_->write64(HE_CTL, he_ctl_.value);
he_ctl_.Start = 1;
host_exe_->write64(HE_CTL, he_ctl_.value);
void he_start_test() {
// start test
he_ctl_.Start = 0;
host_exe_->write64(HE_CTL, he_ctl_.value);
he_ctl_.Start = 1;
host_exe_->write64(HE_CTL, he_ctl_.value);
}

bool verify_numa_node() {
Expand All @@ -272,7 +283,7 @@ class he_cmd : public test_command {
}

int n = numa_max_node();
cout << "There are %d nodes on your system:" << n + 1 << endl;
cout << "Number nodes on system:" << n + 1 << endl;

int numa_node = numa_node_of_cpu(sched_getcpu());
cout << "HE Cache app numa node:" << numa_node << endl;
Expand Down
5 changes: 2 additions & 3 deletions samples/cxl_host_exerciser/cxl_host_exerciser.h
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Original file line number Diff line number Diff line change
Expand Up @@ -334,9 +334,8 @@ const std::map<std::string, uint32_t> he_targets = {

// Bias support
const std::map<std::string, uint32_t> he_bias = {
{"hostmem", HOSTMEM_BIAS},
{"fpgamem_host_bias", FPGAMEM_HOST_BIAS},
{"fpgamem_device_bias", FPGAMEM_DEVICE_BIAS},
{"host", HOSTMEM_BIAS},
{"device", FPGAMEM_DEVICE_BIAS},
};

// he cxl cache device instance
Expand Down
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