Fix several user clock configuration bugs:

- Agilex slow clock was limited to 600MHz instead of 800MHz because the
  wrong parameters were tested.
- Write a new setting even if the clock is not locked. This makes it possible
  to recover from a previous failure.
- Extreme frequency changes sometimes result in configuration failures.
  Program an intermediate frequency before setting the actual target.

binaries/userclk/main.c

@@ -165,13 +165,14 @@ int main(int argc, char *argv[])
 	ON_ERR_GOTO(result, out_destroy_prop, "opening accelerator");
 
 	res = fpgaGetUserClock(accelerator_handle, &userclk_high, &userclk_low, 0);
-	ON_ERR_GOTO(res, out_close, "Failed to get user clock");
+	ON_ERR_GOTO(res, cur_clock_invalid, "Failed to get user clock");
 
 	printf("\nApproximate frequency:\n"
 		"High clock = %5.1f MHz\n"
 		"Low clock  = %5.1f MHz\n \n",
 		userclk_high / 1.0e6, userclk_low / 1.0e6);
 
+cur_clock_invalid:
 	if (userclkCmdLine.freq_high <= -1 &&  userclkCmdLine.freq_low <= -1) {
 		goto out_close;
 	}

libraries/plugins/xfpga/usrclk/fpga_user_clk.c

@@ -660,6 +660,10 @@ fpga_result set_userclock(const char *sysfs_path,
 	ssize_t bytes_written              = 0;
 	struct opae_uio uio;
 
+	unsigned int iopll_max_freq        = IOPLL_MAX_FREQ;
+	unsigned int iopll_min_freq        = IOPLL_MIN_FREQ;
+	unsigned int slow_freq             = MIN_FPGA_FREQ;
+
 	memset(&uio, 0, sizeof(uio));
 
 	if (sysfs_path == NULL) {
@@ -676,9 +680,12 @@ fpga_result set_userclock(const char *sysfs_path,
 	// S10 & A10 user clock DFH revision 0
 	result = get_userclk_revision(sysfs_path, &revision);
 	if (result == FPGA_OK && revision == AGILEX_USRCLK_REV) {
+		iopll_max_freq = IOPLL_AGILEX_MAX_FREQ;
+		iopll_min_freq = IOPLL_AGILEX_MIN_FREQ;
+
 		// Enforce 1x clock within valid range
-		if ((userclk_low > IOPLL_AGILEX_MAX_FREQ) ||
-			(userclk_low < IOPLL_AGILEX_MIN_FREQ)) {
+		if ((userclk_low > iopll_max_freq) ||
+			(userclk_low < iopll_min_freq)) {
 			OPAE_ERR("Invalid Input frequency");
 			return FPGA_INVALID_PARAM;
 		}
@@ -687,14 +694,23 @@ fpga_result set_userclock(const char *sysfs_path,
 	} else {
 		// S10 & A10 user clock
 		// Enforce 1x clock within valid range
-		if ((userclk_low > IOPLL_MAX_FREQ) ||
-			(userclk_low < IOPLL_MIN_FREQ)) {
+		if ((userclk_low > iopll_max_freq) ||
+			(userclk_low < iopll_min_freq)) {
 			OPAE_ERR("Invalid Input frequency");
 			return FPGA_INVALID_PARAM;
 		}
 		bufp = (char *)&iopll_freq_config[userclk_low];
 	}
 
+	// Transitions from a currently configured very high frequency
+	// or very low frequency to another extreme frequency sometimes
+	// fails to stabilize. Start by forcing the fast clock to half
+	// speed.
+	slow_freq = iopll_max_freq / 4;
+	if (userclk_low != slow_freq) {
+		result = set_userclock(sysfs_path, slow_freq * 2, slow_freq);
+	}
+
 	ret = using_iopll(sysfs_usrpath, sysfs_path);
 	if (ret == FPGA_OK) {
 
@@ -720,8 +736,8 @@ fpga_result set_userclock(const char *sysfs_path,
 	}
 
 	struct pll_config *iopll_config = (struct pll_config *)bufp;
-	if ((iopll_config->pll_freq_khz > IOPLL_MAX_FREQ * 1000) ||
-		(iopll_config->pll_freq_khz < IOPLL_MIN_FREQ * 1000))
+	if ((iopll_config->pll_freq_khz > iopll_max_freq * 1000) ||
+		(iopll_config->pll_freq_khz < iopll_min_freq * 1000))
 		return FPGA_EXCEPTION;
 
 	result = get_usrclk_uio(sysfs_path,