Skip to content

Commit

Permalink
Fix: Remove latency iterations from write cache hit/miss scenario tes…
Browse files Browse the repository at this point in the history 
…ts (#3043)

- CXL host exerciser Remove latency iterations tests from write cache hit/miss scenario
   - Remove Bandwidth calculation and output in Read cache hit/miss scenario

Signed-off-by: anandaravuri <ananda.ravuri@intel.com>
  • Loading branch information
@anandaravuri
anandaravuri committed Nov 16, 2023
1 parent bfecf48 commit 3a8b50e
Show file tree
Hide file tree
Showing 4 changed files with 41 additions and 185 deletions.
209 changes: 26 additions & 183 deletions samples/cxl_host_exerciser/cxl_he_cache_cmd.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -239,10 +239,8 @@ class he_cache_cmd : public he_cmd {
he_perf_counters(HE_CXL_RD_LATENCY);

} else if(he_latency_iterations_ > 0) {

// Latency iterations test
double perf_data = 0;
double latency = 0;
double total_perf_data = 0;
double total_latency = 0;

rd_table_ctl_.enable_address_stride = 1;
Expand All @@ -265,18 +263,14 @@ class he_cache_cmd : public he_cmd {
return -1;
}

if (he_get_perf(&perf_data, &latency, HE_CXL_RD_LATENCY)) {
total_perf_data = total_perf_data + perf_data;
total_latency = total_latency + latency;
}
host_exe_->logger_->info("Iteration: {0} latency: {1:0.3f} nanoseconds \
BandWidth: {2:0.3f} GB/s", i, latency, perf_data);
total_latency = total_latency + get_ticks();
host_exe_->logger_->info("Iteration: {0} Latency: {1:0.3f} nanoseconds",
i, (double)(get_ticks() * LATENCY_FACTOR));
} //end for loop

total_latency = total_latency * LATENCY_FACTOR;
host_exe_->logger_->info("Average Latency: {0:0.3f} nanoseconds",
total_latency / he_latency_iterations_);
host_exe_->logger_->info("Average BandWidth: {0:0.3f} GB/s",
total_perf_data / he_latency_iterations_);

} else {
// fpga read cache hit test
host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value);
Expand Down Expand Up @@ -424,39 +418,6 @@ class he_cache_cmd : public he_cmd {
// performance
he_perf_counters();

} else if (he_latency_iterations_ > 0) {
// Latency iterations test
double perf_data = 0;
double total_perf_data = 0;

wr_table_ctl_.enable_address_stride = 1;
wr_table_ctl_.stride = 1;
host_exe_->write64(HE_WR_NUM_LINES, 1);
host_exe_->write64(HE_WR_CONFIG, he_wr_cfg_.value);
host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, wr_table_ctl_.value);

for (uint64_t i = 0; i < he_latency_iterations_; i++) {
// Start test
he_start_test();

// wait for completion
if (!he_wait_test_completion()) {
he_perf_counters();
host_exerciser_errors();
host_exe_->free_cache_read_write();
host_exe_->free_dsm();
return -1;
}

if (he_get_perf(&perf_data, NULL)) {
total_perf_data = total_perf_data + perf_data;
}
host_exe_->logger_->info("Iteration: {0} BandWidth: {2:0.3f} GB/s",
i, perf_data);
} //end for loop
host_exe_->logger_->info("Average BandWidth: {0:0.3f} GB/s",
total_perf_data / he_latency_iterations_);

} else {
// fpga Write cache hit test
host_exe_->write64(HE_WR_CONFIG, he_wr_cfg_.value);
Expand Down Expand Up @@ -512,7 +473,7 @@ class he_cache_cmd : public he_cmd {
he_rd_cfg_.value = 0;
he_rd_cfg_.line_repeat_count = he_linerep_count_;
he_rd_cfg_.read_traffic_enable = 1;
he_rd_cfg_.opcode = RD_LINE_S;
he_rd_cfg_.opcode = RD_LINE_I;

// set RD_ADDR_TABLE_CTRL
rd_table_ctl_.value = 0;
Expand Down Expand Up @@ -559,9 +520,6 @@ class he_cache_cmd : public he_cmd {
} else if (he_latency_iterations_ > 0) {

// Latency loop test
double perf_data = 0;
double latency = 0;
double total_perf_data = 0;
double total_latency = 0;

rd_table_ctl_.enable_address_stride = 1;
Expand All @@ -583,17 +541,14 @@ class he_cache_cmd : public he_cmd {
return -1;
}

if (he_get_perf(&perf_data, &latency, HE_CXL_RD_LATENCY)) {
total_perf_data = total_perf_data + perf_data;
total_latency = total_latency + latency;
}
host_exe_->logger_->info("Iteration: {0} latency: {1:0.3f} nanoseconds \
BandWidth: {2:0.3f} GB/s", i, latency, perf_data);
} // end for loop
total_latency = total_latency + get_ticks();
host_exe_->logger_->info("Iteration: {0} Latency: {1:0.3f} nanoseconds",
i, (double)(get_ticks() * LATENCY_FACTOR));
} //end for loop

total_latency = total_latency * LATENCY_FACTOR;
host_exe_->logger_->info("Average Latency: {0:0.3f} nanoseconds",
total_latency / he_latency_iterations_);
host_exe_->logger_->info("Average BandWidth: {0:0.3f} GB/s",
total_perf_data / he_latency_iterations_);

} else {
// fpga read cache hit test
Expand Down Expand Up @@ -694,39 +649,6 @@ class he_cache_cmd : public he_cmd {
// performance
he_perf_counters();

} else if (he_latency_iterations_ > 0) {
// Latency loop test
double perf_data = 0;
double total_perf_data = 0;

wr_table_ctl_.enable_address_stride = 1;
wr_table_ctl_.stride = 1;
host_exe_->write64(HE_WR_NUM_LINES, 1);
host_exe_->write64(HE_WR_CONFIG, he_wr_cfg_.value);
host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, wr_table_ctl_.value);

for (uint64_t i = 0; i < he_latency_iterations_; i++) {
// Start test
he_start_test();

// wait for completion
if (!he_wait_test_completion()) {
he_perf_counters();
host_exerciser_errors();
host_exe_->free_cache_write();
host_exe_->free_dsm();
return -1;
}

if (he_get_perf(&perf_data, NULL)) {
total_perf_data = total_perf_data + perf_data;
}
host_exe_->logger_->info("Iteration: {0} BandWidth: {2:0.3f} GB/s",
i, perf_data);
} //end for loop
host_exe_->logger_->info("Average BandWidth: {0:0.3f} GB/s",
total_perf_data / he_latency_iterations_);

} else {
// fpga Write cache hit test
host_exe_->write64(HE_WR_CONFIG, he_wr_cfg_.value);
Expand Down Expand Up @@ -782,7 +704,7 @@ class he_cache_cmd : public he_cmd {
he_rd_cfg_.value = 0;
he_rd_cfg_.line_repeat_count = he_linerep_count_;
he_rd_cfg_.read_traffic_enable = 1;
he_rd_cfg_.opcode = RD_LINE_I;
he_rd_cfg_.opcode = RD_LINE_S;
host_exe_->write64(HE_RD_CONFIG, he_rd_cfg_.value);

// set RD_ADDR_TABLE_CTRL
Expand Down Expand Up @@ -825,10 +747,8 @@ class he_cache_cmd : public he_cmd {
he_perf_counters(HE_CXL_RD_LATENCY);

} else if (he_latency_iterations_ > 0) {

// Latency loop test
double perf_data = 0;
double latency = 0;
double total_perf_data = 0;
double total_latency = 0;

rd_table_ctl_.enable_address_stride = 1;
Expand All @@ -854,17 +774,14 @@ class he_cache_cmd : public he_cmd {
return -1;
}

if (he_get_perf(&perf_data, &latency, HE_CXL_RD_LATENCY)) {
total_perf_data = total_perf_data + perf_data;
total_latency = total_latency + latency;
}
host_exe_->logger_->info("Iteration: {0} latency: {1:0.3f} nanoseconds \
BandWidth: {2:0.3f} GB/s", i, latency, perf_data);
total_latency = total_latency + get_ticks();
host_exe_->logger_->info("Iteration: {0} Latency: {1:0.3f} nanoseconds",
i, (double)(get_ticks() * LATENCY_FACTOR));
} //end for loop

total_latency = total_latency * LATENCY_FACTOR;
host_exe_->logger_->info("Average Latency: {0:0.3f} nanoseconds",
total_latency / he_latency_iterations_);
host_exe_->logger_->info("Average BandWidth: {0:0.3f} GB/s",
total_perf_data / he_latency_iterations_);

} else {
// fpga read cache hit test
Expand Down Expand Up @@ -969,42 +886,6 @@ class he_cache_cmd : public he_cmd {
// performance
he_perf_counters();

} else if (he_latency_iterations_ > 0) {
// Latency loop test
double perf_data = 0;
double total_perf_data = 0;

wr_table_ctl_.enable_address_stride = 1;
wr_table_ctl_.stride = 1;
host_exe_->write64(HE_WR_NUM_LINES, 1);
host_exe_->write64(HE_WR_CONFIG, he_wr_cfg_.value);
host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, wr_table_ctl_.value);

for (uint64_t i = 0; i < he_latency_iterations_; i++) {
// Start test
he_start_test();

// wait for completion
if (!he_wait_test_completion()) {
he_perf_counters();
host_exerciser_errors();
g_stop_thread = true;
t1.join();
sleep(1);
host_exe_->free_cache_write();
host_exe_->free_dsm();
return -1;
}

if (he_get_perf(&perf_data, NULL)) {
total_perf_data = total_perf_data + perf_data;
}
host_exe_->logger_->info("Iteration: {0} BandWidth: {2:0.3f} GB/s",
i, perf_data);
} // end for loop
host_exe_->logger_->info("Average BandWidth: {0:0.3f} GB/s",
total_perf_data / he_latency_iterations_);

} else {
// fpga Write cache hit test
host_exe_->write64(HE_WR_CONFIG, he_wr_cfg_.value);
Expand Down Expand Up @@ -1103,10 +984,8 @@ class he_cache_cmd : public he_cmd {
he_perf_counters(HE_CXL_RD_LATENCY);

} else if (he_latency_iterations_ > 0) {

// Latency loop test
double perf_data = 0;
double latency = 0;
double total_perf_data = 0;
double total_latency = 0;

rd_table_ctl_.enable_address_stride = 1;
Expand All @@ -1129,17 +1008,14 @@ class he_cache_cmd : public he_cmd {
return -1;
}

if (he_get_perf(&perf_data, &latency, HE_CXL_RD_LATENCY)) {
total_perf_data = total_perf_data + perf_data;
total_latency = total_latency + latency;
}
host_exe_->logger_->info("Iteration: {0} latency: {1:0.3f} nanoseconds \
BandWidth: {2:0.3f} GB/s", i, latency, perf_data);
total_latency = total_latency + get_ticks();
host_exe_->logger_->info("Iteration: {0} Latency: {1:0.3f} nanoseconds",
i, (double)(get_ticks() * LATENCY_FACTOR));
} //end for loop

total_latency = total_latency * LATENCY_FACTOR;
host_exe_->logger_->info("Average Latency: {0:0.3f} nanoseconds",
total_latency / he_latency_iterations_);
host_exe_->logger_->info("Average BandWidth: {0:0.3f} GB/s",
total_perf_data / he_latency_iterations_);

} else {
// fpga read cache hit test
Expand Down Expand Up @@ -1233,39 +1109,6 @@ class he_cache_cmd : public he_cmd {
// performance
he_perf_counters();

} else if (he_latency_iterations_ > 0) {
// Latency loop test
double perf_data = 0;
double total_perf_data = 0;

wr_table_ctl_.enable_address_stride = 1;
wr_table_ctl_.stride = 1;
host_exe_->write64(HE_WR_NUM_LINES, 1);
host_exe_->write64(HE_WR_CONFIG, he_wr_cfg_.value);
host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, wr_table_ctl_.value);

for (uint64_t i = 0; i < he_latency_iterations_; i++) {
// Start test
he_start_test();

// wait for completion
if (!he_wait_test_completion()) {
he_perf_counters();
host_exerciser_errors();
host_exe_->free_cache_write();
host_exe_->free_dsm();
return -1;
}

if (he_get_perf(&perf_data, NULL)) {
total_perf_data = total_perf_data + perf_data;
}
host_exe_->logger_->info("Iteration: {0} BandWidth: {2:0.3f} GB/s",
i, perf_data);
} // end for loop
host_exe_->logger_->info("Average BandWidth: {0:0.3f} GB/s",
total_perf_data / he_latency_iterations_);

} else {
// fpga Write cache hit test
host_exe_->write64(HE_WR_CONFIG, he_wr_cfg_.value);
Expand Down
12 changes: 12 additions & 0 deletions samples/cxl_host_exerciser/cxl_he_cmd.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -326,6 +326,18 @@ class he_cmd : public test_command {
return false;
}

uint64_t get_ticks() {
volatile he_cache_dsm_status* dsm_status = NULL;

dsm_status = reinterpret_cast<he_cache_dsm_status*>(
(uint8_t*)(host_exe_->get_dsm()));
if (!dsm_status)
return 0;
if (dsm_status->num_ticks > 0)
return dsm_status->num_ticks;
else
return 0;
}

protected:
host_exerciser *host_exe_;
Expand Down
1 change: 1 addition & 0 deletions samples/cxl_host_exerciser/cxl_host_exerciser.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,7 @@ static const uint64_t BUFFER_SIZE_32KB = 32* KB;
static const uint64_t FPGA_32KB_CACHE_LINES = (32 * KB) / 64;
static const uint64_t FPGA_2MB_CACHE_LINES = (2 * MB) / 64;
static const uint64_t FPGA_512CACHE_LINES = 512;
static const double LATENCY_FACTOR = 2.5;

// Host execiser CSR Offset
enum {
Expand Down
4 changes: 2 additions & 2 deletions samples/cxl_host_exerciser/he_cache_test.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -772,7 +772,7 @@ class afu {
goto out_free;
}

logger_->debug("nDFL_CXL_CACHE_WR_ADDR_TABLE_DATA : 0x:{0:x}", *u64_rd);
logger_->debug("DFL_CXL_CACHE_WR_ADDR_TABLE_DATA : 0x:{0:x}", *u64_rd);
logger_->debug("DFL_CXL_CACHE_WR_ADDR_TABLE_DATA : 0x:{0:x}", *u64_wr);

rd_wr_buffer_ = (uint8_t *)ptr;
Expand Down Expand Up @@ -811,7 +811,7 @@ class afu {
<< endl;
}

logger_->debug("nDFL_CXL_CACHE_WR_ADDR_TABLE_DATA : 0x:{0:x}", *u64_rd);
logger_->debug("DFL_CXL_CACHE_WR_ADDR_TABLE_DATA : 0x:{0:x}", *u64_rd);
logger_->debug("DFL_CXL_CACHE_WR_ADDR_TABLE_DATA : 0x:{0:x}", *u64_wr);

buffer_release(rd_wr_buffer_, rd_wr_buf_len_);
Expand Down

0 comments on commit 3a8b50e

Please sign in to comment.