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4 followers · 7 following
  • Shanghai University
  • Shanghai

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JacoboJin/README.md
 

Hey! Nice to meet you here 👋

Welcome to my Github Page!

I'm Jayce, Digital IC designer from China, currently living in Shanghai.

Things I Code with

Verilog SystemVerilog Python C/C++ Matlab

Github Stats

Jacobo's GitHub stats

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  1. RISCV-on-PYNQ-Z2 RISCV-on-PYNQ-Z2 Public

    This repo is to inplemente the riscv soc on the xilinx pynq-z2 board

    Verilog 10

  2. PANXI-RV32Core PANXI-RV32Core Public

    This is an experiment for lab's members, aiming to design an RV32 SoC. In the future, we will continuously add the desired functions to it.

    SystemVerilog