init test caches

src/abejaruco.v

@@ -30,6 +30,10 @@
 `include "src/execution/execution_registers.v"
 `include "src/execution/mul_registers.v"
 `include "src/fetch/fetch_registers.v"
+
+`include "src/common/priority_encoder.v" 
+`include "src/common/tag_comparator.v"
+`include "src/memory/d_cache.v"
 `include "src/memory/cache.v"
 `include "src/memory/memory.v"
 `include "src/memory/memory_registers.v"
@@ -476,6 +480,63 @@ module Abejaruco #(parameter PROGRAM = "../../programs/zero.o")(
   //               Memory stage                //
   ////----------------------------------------///
 
+  // DCache data_cache(// In
+  //         // -- from CPU
+  //         .clk(clk),
+  //         .reset(reset),
+  //         .access(icache_access),
+  //         .address(icache_address),
+  //         .data_in(icache_data_in),
+  //         .op(icache_op),
+  //         .byte_op(icache_byte_op),
+  //         // -- from main memory
+  //         .mem_data_ready(icache_mem_data_ready),
+  //         .mem_data_out(icache_mem_data_out),
+  //         .memory_in_use(memory_in_use),
+
+  //         // Out
+  //         // -- to CPU
+  //         .data_out(icache_data_out),
+  //         .data_ready(icache_data_ready),
+  //         // -- to main memory
+  //         .mem_op_init(icache_mem_op_init),
+  //         .mem_enable(icache_mem_enable),
+  //         .mem_op(icache_mem_op),
+  //         .mem_op_done(icache_op_done),
+  //         .mem_address(icache_mem_address),
+  //         .mem_data_in(icache_mem_data_in)
+  //       );
+
+  //   module DCache (
+  //   // In wires (from CPU)
+  //   input wire clk,
+  //   input wire access,
+  //   input wire reset,
+  //   input wire [ADDRESS_WIDTH-1:0] address,
+  //   input wire [WORD_WIDTH-1:0] data_in,        // Data to be written in the cache
+  //   input wire op,
+  //   input wire byte_op,
+
+  //   // In wires (from memory)
+  //   input wire mem_data_ready,
+  //   input wire [CACHE_LINE_SIZE-1:0] mem_data_out,
+  //   input wire memory_in_use,
+
+  //   // Out wires (to CPU)
+  //   output reg [WORD_WIDTH-1:0] data_out,       // Data returned by the cache
+  //   output wire data_ready,                     // Data in the output is valid or write operation finished
+
+  //   // Out wires (to memory)
+  //   output reg mem_enable,                      // Enable the memory module to read/write
+  //   output reg mem_op,                          // Select read/write operation
+  //   output reg mem_op_init,                     // Tell memory that we are going to use it
+  //   output reg mem_op_done,                     // The caché finished reading the returned data
+  //   output reg [CACHE_LINE_SIZE-1:0] mem_data_in,     // Data to be written in memory
+  //   output reg [MEMORY_ADDRESS_SIZE-1:0] mem_address  // Address to be read/written in memory
+  // );
+
+
+
   MemoryRegisters memory_registers(
                     // In
                     .clk(clk),

src/common/priority_encoder.v

@@ -19,6 +19,9 @@
 // along with Abejaruco placed on the LICENSE.md file of the root folder.
 // If not, see <https:// www.gnu.org/licenses/>.
 
+`ifndef PRIORITY_ENCODER_V
+`define PRIORITY_ENCODER_V
+
 module priority_encoder(
     input wire [3:0] hit,
     output reg [1:0] line_number
@@ -33,3 +36,5 @@ module priority_encoder(
         endcase
     end
 endmodule
+
+`endif

src/common/tag_comparator.v

@@ -19,6 +19,9 @@
 // along with Abejaruco placed on the LICENSE.md file of the root folder.
 // If not, see <https:// www.gnu.org/licenses/>.
 
+`ifndef TAG_COMPARATOR_V
+`define TAG_COMPARATOR_V
+
 module tag_comparator(
     input wire [TAG_WIDTH-1:0] input_tag,
     input wire [TAG_WIDTH-1:0] stored_tag,
@@ -29,3 +32,5 @@ module tag_comparator(
 
   assign hit = valid ? (input_tag == stored_tag) : 1'b0;
 endmodule
+
+`endif

src/memory/CMakeLists.txt

@@ -20,7 +20,7 @@
 
 include(AddModule)
 
-list(APPEND VERILOG_MODULES memory cache)
+list(APPEND VERILOG_MODULES memory cache d_cache)
 
 foreach(MODULE IN ITEMS ${VERILOG_MODULES})
   add_module(TARGET ${MODULE} INCLUDES "${PROJECT_SOURCE_DIR}")

src/memory/cache.v

@@ -18,7 +18,9 @@
 // You should have received a copy of the GNU General Public License
 // along with Abejaruco placed on the LICENSE.md file of the root folder.
 // If not, see <https:// www.gnu.org/licenses/>.
-`include "src/common/priority_encoder.v"
+
+
+`include "src/common/priority_encoder.v" 
 `include "src/common/tag_comparator.v"
 
 //TODO add half word operations

tests/program_tests/CMakeLists.txt

@@ -21,7 +21,7 @@
 
 include(AddModule)
 
-list(APPEND VERILOG_MODULES alu_ops branch buffer_sum hazards jump load_add)
+list(APPEND VERILOG_MODULES alu_ops branch buffer_sum dcache_acceses hazards jump load_add)
 
 foreach(MODULE IN ITEMS ${VERILOG_MODULES})
   add_module(TARGET "${MODULE}.tb" INCLUDES "${PROJECT_SOURCE_DIR}")

tests/program_tests/alu_ops.tb.v

@@ -60,4 +60,9 @@ module ALUOps_tb();
     $finish;
   end
 
-endmodule
+  always
+  begin
+    #CLK_PERIOD clk = ~clk;
+  end
+
+endmodule