💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation

TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems

RISC-V Virtual Prototype

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

A modeling library with virtual components for SystemC and TLM simulators