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A repository that aims to provide tools for cryptography and cryptanalysis

HTML 200 50 Updated Jun 24, 2020
VHDL 3 Updated Dec 11, 2017
SystemVerilog 16 1 Updated Nov 7, 2019

IEEE P1735 decryptor for VHDL

Python 24 11 Updated Jun 23, 2015
Verilog 1 1 Updated Dec 23, 2016
Verilog 1 Updated Jul 26, 2022

commit rtl and build cosim env

Verilog 13 Updated Feb 15, 2024
Verilog 6 1 Updated Sep 12, 2023

QEMU libsystemctlm-soc co-simulation demos.

C++ 117 46 Updated May 30, 2024

OpenXuantie - OpenC910 Core

Verilog 1,143 301 Updated Jun 28, 2024

RDMA core userspace libraries and daemons

C 3 4 Updated Oct 24, 2021

PCIe (1.0a to 2.0) Virtual host model for verilog

C 77 21 Updated Aug 23, 2024

PCIE 5.0 Graduation project (Verification Team)

Verilog 53 22 Updated Jan 27, 2024

List of awesome open source hardware tools, generators, and reusable designs

Python 1,864 168 Updated Aug 31, 2024

A List of Free and Open Source Hardware Verification Tools and Frameworks

482 46 Updated Sep 8, 2023

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Python 1 1 Updated Jul 13, 2023

Verification of 128-bit AES Pipelined Cipher block using UVM methodology

Verilog 3 1 Updated Jun 7, 2019

signature algorithm,Interface security verification。

Go 10 5 Updated Nov 20, 2020

Formal verification of Advanced Encryption Standard (AES)

SystemVerilog 1 Updated Feb 25, 2023
SystemVerilog 1 Updated Mar 18, 2023

System on Chip verified with UVM/OSVVM/FV

SystemVerilog 23 6 Updated Sep 26, 2024

lowRISC Style Guides

1 Updated Dec 15, 2023

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,344 523 Updated Sep 23, 2024

Powerful, fast and robust engine for converting 3D models into g-code instructions for 3D printers. It is part of the larger open source project Cura.

C++ 1,676 880 Updated Sep 25, 2024

VUnit is a unit testing framework for VHDL/SystemVerilog

VHDL 722 260 Updated Sep 16, 2024

GPGPU microprocessor architecture

C 1,989 351 Updated Apr 26, 2024

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Python 1,757 503 Updated Sep 27, 2024

The root repo for lowRISC project and FPGA demos.

SystemVerilog 596 148 Updated Aug 3, 2023