From 91758f36edaf9b1afcb17ec34f29b63f33d9c2a9 Mon Sep 17 00:00:00 2001 From: ZhangZifei <1773908404@qq.com> Date: Sat, 10 Oct 2020 14:42:42 +0800 Subject: [PATCH 1/6] PTE: disable pte a/d update when SHARE --- src/isa/riscv64/mmu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/isa/riscv64/mmu.c b/src/isa/riscv64/mmu.c index 9115080cd..4fb4930ea 100644 --- a/src/isa/riscv64/mmu.c +++ b/src/isa/riscv64/mmu.c @@ -104,12 +104,14 @@ static paddr_t ptw(vaddr_t vaddr, int type) { pg_base = (pg_base & ~pg_mask) | (vaddr & pg_mask & ~PGMASK); } +#if !_SHARE bool is_write = (type == MEM_TYPE_WRITE); if (!pte.a || (!pte.d && is_write)) { pte.a = true; pte.d |= is_write; paddr_write(p_pte, pte.val, PTE_SIZE); } +#endif return pg_base | MEM_RET_OK; } From cd5c2fcde42f8ef1b07370c3f338a6e2007f58c3 Mon Sep 17 00:00:00 2001 From: William Wang Date: Mon, 12 Oct 2020 19:27:09 +0800 Subject: [PATCH 2/6] riscv64: check SPF before sc vaddr compare --- src/isa/riscv64/exec/amo.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/isa/riscv64/exec/amo.h b/src/isa/riscv64/exec/amo.h index 57a9a2852..702ad0cc9 100644 --- a/src/isa/riscv64/exec/amo.h +++ b/src/isa/riscv64/exec/amo.h @@ -13,6 +13,17 @@ static inline make_EHelper(lr) { static inline make_EHelper(sc) { // should check overlapping instead of equality // printf("sc: cpu.lr_addr %lx (%lx) addr %lx\n", cpu.lr_addr, cpu.lr_valid, *dsrc1); + + // Even if scInvalid, SPF (if raised) also needs to be reported + { + int ret = isa_vaddr_check(*dsrc1, MEM_TYPE_WRITE, s->width); + if (ret == MEM_RET_OK); + // pass + else if (ret == MEM_RET_NEED_TRANSLATE) + if(isa_mmu_translate(*dsrc1, MEM_TYPE_WRITE, s->width) == MEM_RET_FAIL) + return_on_mem_ex(); + } + if (cpu.lr_addr == *dsrc1 && cpu.lr_valid) { rtl_sm(s, dsrc1, 0, dsrc2, s->width); return_on_mem_ex(); From ec29357dd54555bfbb2ed2853ff9bbb37c6e3547 Mon Sep 17 00:00:00 2001 From: William Wang Date: Mon, 12 Oct 2020 21:49:05 +0800 Subject: [PATCH 3/6] Difftest: add set / get all CSRs api --- include/isa.h | 3 +++ src/isa/riscv64/difftest/ref.c | 8 ++++++++ src/isa/riscv64/reg.c | 2 +- src/monitor/difftest/ref.c | 8 ++++++++ 4 files changed, 20 insertions(+), 1 deletion(-) diff --git a/include/isa.h b/include/isa.h index 01039761c..ef7a37811 100644 --- a/include/isa.h +++ b/include/isa.h @@ -14,6 +14,7 @@ void init_isa(); // reg extern CPU_state cpu; +extern rtlreg_t csr_array[4096]; void isa_reg_display(); word_t isa_reg_str2val(const char *name, bool *success); @@ -41,6 +42,8 @@ void isa_difftest_setregs(const void *r); void isa_difftest_raise_intr(word_t NO); void isa_difftest_get_mastatus(void *s); void isa_difftest_set_mastatus(const void *s); +void isa_difftest_get_csr(void *c); +void isa_difftest_set_csr(const void *c); vaddr_t isa_disambiguate_exec(void *disambiguate_para); bool isa_difftest_microarchitectural_pf_check(vaddr_t addr); diff --git a/src/isa/riscv64/difftest/ref.c b/src/isa/riscv64/difftest/ref.c index 6fb74c6f5..a84b499b4 100644 --- a/src/isa/riscv64/difftest/ref.c +++ b/src/isa/riscv64/difftest/ref.c @@ -71,6 +71,14 @@ void isa_difftest_set_mastatus(const void *s) { cpu.lr_valid = ms->lrscValid; } +void isa_difftest_set_csr(const void *c) { + memcpy(csr_array, c, 4096 * sizeof(rtlreg_t)); +} + +void isa_difftest_get_csr(void *c) { + memcpy(c, csr_array, 4096 * sizeof(rtlreg_t)); +} + void isa_difftest_raise_intr(word_t NO) { DecodeExecState s; s.is_jmp = 0; diff --git a/src/isa/riscv64/reg.c b/src/isa/riscv64/reg.c index 34a18c40a..388aa6d95 100644 --- a/src/isa/riscv64/reg.c +++ b/src/isa/riscv64/reg.c @@ -45,7 +45,7 @@ rtlreg_t isa_reg_str2val(const char *s, bool *success) { return 0; } -static word_t csr_array[4096] = {}; +rtlreg_t csr_array[4096] = {}; #define CSRS_DEF(name, addr) \ concat(name, _t)* const name = (void *)&csr_array[addr]; diff --git a/src/monitor/difftest/ref.c b/src/monitor/difftest/ref.c index b2dcf89e4..4cd22dfa1 100644 --- a/src/monitor/difftest/ref.c +++ b/src/monitor/difftest/ref.c @@ -29,6 +29,14 @@ void difftest_set_mastatus(const void *s){ isa_difftest_set_mastatus(s); } +void difftest_get_csr(void *c){ + isa_difftest_get_csr(c); +} + +void difftest_set_csr(const void *c){ + isa_difftest_set_csr(c); +} + vaddr_t disambiguate_exec(void *disambiguate_para){ return isa_disambiguate_exec(disambiguate_para); } From a5b2d8e2b029c99693ba2f076fc0fcb7a95c6b5a Mon Sep 17 00:00:00 2001 From: William Wang Date: Wed, 14 Oct 2020 11:01:16 +0800 Subject: [PATCH 4/6] Difftest: add lrAddr into snapshot --- src/isa/riscv64/difftest/difftest.h | 1 + src/isa/riscv64/difftest/ref.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/isa/riscv64/difftest/difftest.h b/src/isa/riscv64/difftest/difftest.h index 6184ba4c7..be590781d 100644 --- a/src/isa/riscv64/difftest/difftest.h +++ b/src/isa/riscv64/difftest/difftest.h @@ -9,6 +9,7 @@ void isa_difftest_setregs_hook(void); struct SyncState { uint64_t lrscValid; + uint64_t lrscAddr; }; #endif diff --git a/src/isa/riscv64/difftest/ref.c b/src/isa/riscv64/difftest/ref.c index a84b499b4..086f966fd 100644 --- a/src/isa/riscv64/difftest/ref.c +++ b/src/isa/riscv64/difftest/ref.c @@ -63,12 +63,14 @@ void isa_difftest_setregs(const void *r) { void isa_difftest_get_mastatus(void *s) { struct SyncState ms; ms.lrscValid = cpu.lr_valid; + ms.lrscAddr = cpu.lr_addr; memcpy(s, &ms, sizeof(struct SyncState)); } void isa_difftest_set_mastatus(const void *s) { struct SyncState* ms = (struct SyncState*)s; cpu.lr_valid = ms->lrscValid; + cpu.lr_addr = ms->lrscAddr; } void isa_difftest_set_csr(const void *c) { From 8363ec3a8b09d2d951d130ef96a6176aead0b263 Mon Sep 17 00:00:00 2001 From: William Wang Date: Thu, 22 Oct 2020 11:09:30 +0800 Subject: [PATCH 5/6] Difftest: add xtval to DisambiguationState * It will help NEMU force IPF treat cross-page IPF correctly --- include/isa/riscv64.h | 4 +++- src/isa/riscv64/mmu.c | 19 +++++++++++++++++-- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/include/isa/riscv64.h b/include/isa/riscv64.h index 11c92eb28..65bd011c2 100644 --- a/include/isa/riscv64.h +++ b/include/isa/riscv64.h @@ -12,11 +12,13 @@ #define riscv64_PMEM_BASE 0x80000000 // #define ENABLE_DISAMBIGUATE -// #define FORCE_RAISE_PF +#define FORCE_RAISE_PF // reg struct DisambiguationState { uint64_t exceptionNo; + uint64_t mtval; + uint64_t stval; }; typedef struct { diff --git a/src/isa/riscv64/mmu.c b/src/isa/riscv64/mmu.c index 4fb4930ea..d4fd39fb9 100644 --- a/src/isa/riscv64/mmu.c +++ b/src/isa/riscv64/mmu.c @@ -121,8 +121,23 @@ int force_raise_pf(vaddr_t vaddr, int type){ if(cpu.need_disambiguate){ if(ifetch && cpu.disambiguation_state.exceptionNo == EX_IPF){ - if (cpu.mode == MODE_M) mtval->val = vaddr; - stval->val = vaddr; + if (cpu.mode == MODE_M) { + mtval->val = cpu.disambiguation_state.mtval; + if(vaddr != cpu.disambiguation_state.mtval){ + printf("[WRANING] nemu mtval %lx does not match core mtval %lx\n", + vaddr, + cpu.disambiguation_state.mtval + ); + } + } else { + stval->val = cpu.disambiguation_state.stval; + if(vaddr != cpu.disambiguation_state.stval){ + printf("[WRANING] nemu stval %lx does not match core stval %lx\n", + vaddr, + cpu.disambiguation_state.stval + ); + } + } cpu.mem_exception = EX_IPF; printf("force raise IPF\n"); return MEM_RET_FAIL; From c23548d626e9e40eb102c264bd2f7a77e1f37a55 Mon Sep 17 00:00:00 2001 From: Yinan Xu Date: Mon, 26 Oct 2020 20:25:47 +0800 Subject: [PATCH 6/6] exec: decode opcode6_2 021,022 to fp --- src/isa/riscv64/exec/exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/isa/riscv64/exec/exec.c b/src/isa/riscv64/exec/exec.c index 0f131d4e5..4ec0877ba 100644 --- a/src/isa/riscv64/exec/exec.c +++ b/src/isa/riscv64/exec/exec.c @@ -189,7 +189,7 @@ static inline void exec(DecodeExecState *s) { IDEX (004, I, op_imm) IDEX (005, U, auipc) IDEX (006, I, op_imm32) IDEX (010, S, store) EX (011, fp) IDEX (013, R, atomic) IDEX (014, R, op) IDEX (015, U, lui) IDEX (016, R, op32) - EX (020, fp) + EX (020, fp) EX (021, fp) EX (022, fp) EX (024, fp) IDEX (030, B, branch) IDEX (031, I, jalr) EX (032, nemu_trap) IDEX (033, J, jal) EX (034, system)