VLSI EDA Global Router
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Updated
Jan 22, 2018 - C++
VLSI EDA Global Router
Two Address Instructions (16bit) CPU
A SAT-Based cell router.
A LEF/DEF Utility.
reproduction paper research in low voltage clock tree design
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
Latex source files for a research paper on improving placement algorithms used in VLSI design process
Animation of VLSI Placement/Floorplanning using Simulated Annealing or Iterative Improvement
Visualization of VLSI Maze Routing Algorithms (Lee, Hadlock, A*)
DATC RDF
VLSI Design, Magic, OpenCircuitDesign,CMOS VLSI Design, CMOS Inverter Magic
A simple tool to demonstrate the physical design steps of VLSI Design Flow.
Domain Specific Hardware Accelerators - VLSI CAD Project
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
Some simple examples for the Magic VLSI physical chip layout tool.
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisa…
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