VLSI EDA Global Router
-
Updated
Jan 22, 2018 - C++
VLSI EDA Global Router
A SAT-Based cell router.
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
A customized placer based on the RePlAce global placement tool.
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
Coursework of NTHU CS613500 VLSI Physical Design Automation
Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”
Deep learning toolkit-enabled VLSI placement
Steiner Shallow-Light Tree for VLSI Routing
Add a description, image, and links to the vlsi-physical-design topic page so that developers can more easily learn about it.
To associate your repository with the vlsi-physical-design topic, visit your repo's landing page and select "manage topics."