soc: riscv: Add initial support for GigaDevice GD32V SoC

Add GigaDevice GD32V SoC.
GD32V has non-standard CSR. It doesn't use common startup code.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>

CODEOWNERS

@@ -74,6 +74,7 @@
 /soc/riscv/openisa*/                      @dleach02
 /soc/riscv/riscv-privilege/andes_v5/      @cwshu @kevinwang821020 @jimmyzhe
 /soc/riscv/riscv-privilege/neorv32/       @henrikbrixandersen
+/soc/riscv/riscv-privilege/gd32vf103/     @soburi
 /soc/x86/                                 @dcpleung @nashif @jenmwms @aasthagr
 /arch/xtensa/                             @dcpleung @andyross @nashif
 /soc/xtensa/                              @dcpleung @andyross @nashif

dts/bindings/cpu/nuclei,bumblebee.yaml

@@ -0,0 +1,14 @@
+# Copyright (c) 2021 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuclei Bumblebee RISC-V Core
+
+compatible: "nuclei,bumblebee"
+
+include: cpu.yaml
+
+properties:
+  mcause-exception-mask:
+    type: int
+    required: true
+    description:  Specify the bits to use for exception code in mcause register.

dts/riscv/gigadevice/gd32vf103.dtsi

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/timer/riscv-machine-timer.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu: cpu@0 {
+			clock-frequency = <108000000>;
+			mcause-exception-mask = <0x7ff>;
+			compatible = "nuclei,bumblebee", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "gd,gd32vf103-soc", "simple-bus";
+		ranges;
+
+		mtimer: machine-timer@d1000000 {
+			compatible = "riscv,machine-timer";
+			reg = <0xd1000000 0x1
+			       0xd1000008 0x1>;
+			clk-divider = <RISCV_MACHINE_TIMER_DIVIDER_4>;
+		};
+
+		fmc: flash-controller@40022000 {
+			compatible = "gd,gd32-flash-controller";
+			label = "FMC";
+			reg = <0x40022000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				label = "FLASH0";
+				write-block-size = <2>;
+			};
+		};
+	};
+};

dts/riscv/gigadevice/gd32vf103X8.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <gigadevice/gd32vf103.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(20)>;
+	};
+
+	soc {
+		flash: flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};

dts/riscv/gigadevice/gd32vf103Xb.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <gigadevice/gd32vf103.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash: flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};

soc/riscv/riscv-privilege/gd32vf103/CMakeLists.txt

@@ -0,0 +1,5 @@
+# Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(entry.S)
+zephyr_sources(soc.c)

soc/riscv/riscv-privilege/gd32vf103/Kconfig.defconfig.gd32vf103

@@ -0,0 +1,39 @@
+# Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_GD32VF103
+
+config SOC
+	default "gd32vf103"
+
+config KERNEL_ENTRY
+	default "__nuclei_start"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if RISCV_MACHINE_TIMER
+
+config RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER
+	default $(dt_node_int_prop_int,/soc/machine-timer@d1000000,clk-divider) if RISCV_MACHINE_TIMER
+
+config RISCV_SOC_MCAUSE_EXCEPTION_MASK
+	default $(dt_node_int_prop_hex,/cpus/cpu@0,mcause-exception-mask)
+
+config RISCV_SOC_INTERRUPT_INIT
+	default y
+
+config RISCV_HAS_CPU_IDLE
+	default y
+
+config RISCV_GP
+	default y
+
+config RISCV_HAS_PLIC
+	default n
+
+config NUM_IRQS
+	default 64
+
+config FLASH_BASE_ADDRESS
+	default $(dt_node_reg_addr_hex,flash0@8000000)
+
+endif # GD32VF103

soc/riscv/riscv-privilege/gd32vf103/Kconfig.defconfig.series

@@ -0,0 +1,11 @@
+# Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_GD32VF103
+
+source "soc/riscv/riscv-privilege/gd32vf103/Kconfig.defconfig.gd32vf103*"
+
+config SOC_SERIES
+	default "gd32vf103"
+
+endif # SOC_SERIES_GD32VF103

soc/riscv/riscv-privilege/gd32vf103/Kconfig.series

@@ -0,0 +1,19 @@
+# GD32VF103 SOC implementation
+
+# Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_GD32VF103
+	bool "GigaDevice GD32VF103 series SoC implementation"
+	select RISCV
+	select SOC_FAMILY_RISCV_PRIVILEGE
+	select ATOMIC_OPERATIONS_C
+	select COMPRESSED_ISA
+	select INCLUDE_RESET_VECTOR
+	select BUILD_OUTPUT_HEX
+	select XIP
+	select GD32_HAS_AFIO_PINMUX
+	select HAS_GD32_HAL
+
+	help
+	  Enable support for GigaDevice GD32VF1 series SoC

soc/riscv/riscv-privilege/gd32vf103/Kconfig.soc

@@ -0,0 +1,13 @@
+# GD32VF103 SOC configuration options
+
+# Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "GigaDevice GD32VF103 SOC implementation"
+	depends on SOC_SERIES_GD32VF103
+
+config SOC_GD32VF103
+	bool "GD32VF103"
+
+endchoice

soc/riscv/riscv-privilege/gd32vf103/entry.S

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <toolchain.h>
+#include <arch/riscv/csr.h>
+#include <nuclei/nuclei_csr.h>
+
+GTEXT(__nuclei_start)
+SECTION_FUNC(vectors, __nuclei_start)
+	/* Disable Global Interrupt */
+	csrc mstatus, MSTATUS_MIE
+	/* Jump to logical address first to ensure correct operation of RAM region  */
+	la	a0, __nuclei_start
+	li	a1, 1
+	slli	a1, a1, 29
+	bleu	a1, a0, _start0800
+	srli	a1, a1, 2
+	bleu	a1, a0, _start0800
+	la	a0, _start0800
+	add	a0, a0, a1
+	jr	a0
+
+_start0800:
+
+#if defined(CONFIG_RISCV_GP)
+	/* Initialize global pointer */
+	.option push
+	.option norelax
+	la	gp, __global_pointer$
+	.option pop
+#endif
+
+	.option norvc;
+
+	/* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */
+	li	t0, 0x200
+	csrs	CSR_MMISC_CTL, t0
+
+	/* Initial the CSR MTVEC for the Trap ane NMI base addr */
+	la	t0, trap_entry
+	csrw	mtvec, t0
+
+	/* Direct Mode: All exceptions set pc to BASE. */
+	csrc	mtvec, 0x3
+
+	/* Disable performance counter */
+	csrsi	mcountinhibit, 0x5
+
+	/* Jump to __reset */
+	tail __reset
+
+1:
+	j 1b
+
+.align 6
+trap_entry:
+	tail __irq_wrapper

soc/riscv/riscv-privilege/gd32vf103/linker.ld

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/riscv/common/linker.ld>

soc/riscv/riscv-privilege/gd32vf103/soc.c

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+
+static int gigadevice_gd32v_soc_init(const struct device *dev)
+{
+	uint32_t key;
+
+	ARG_UNUSED(dev);
+
+	key = irq_lock();
+
+	SystemInit();
+
+	irq_unlock(key);
+
+	return 0;
+}
+
+SYS_INIT(gigadevice_gd32v_soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/riscv/riscv-privilege/gd32vf103/soc.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the GigaDevice GD32VF103 processor
+ */
+
+#ifndef RISCV_GD32VF103_SOC_H_
+#define RISCV_GD32VF103_SOC_H_
+
+#include <soc_common.h>
+#include <devicetree.h>
+
+/* Timer configuration */
+#define RISCV_MTIME_BASE      DT_REG_ADDR_BY_IDX(DT_NODELABEL(mtimer), 0)
+#define RISCV_MTIMECMP_BASE   DT_REG_ADDR_BY_IDX(DT_NODELABEL(mtimer), 1)
+
+#ifndef _ASMLANGUAGE
+#include <toolchain.h>
+#include <gd32vf103.h>
+#endif  /* !_ASMLANGUAGE */
+
+#endif  /* RISCV_GD32VF103_SOC_H */