{"payload":{"header_redesign_enabled":false,"results":[{"id":"354816211","archived":false,"color":"#adb2cb","followers":35,"has_funding_file":false,"hl_name":"sy2002/MiSTer2MEGA65","hl_trunc_description":"Framework to simplify porting MiSTer (and other) cores to the MEGA65","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":354816211,"name":"MiSTer2MEGA65","owner_id":6825267,"owner_login":"sy2002","updated_at":"2024-09-21T11:17:13.351Z","has_issues":true}},"sponsorable":false,"topics":["fpga","mister","qnice","mega65","mister-core","misterfpga"],"type":"Public template","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":61,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Asy2002%252FMiSTer2MEGA65%2B%2Blanguage%253AVHDL","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/sy2002/MiSTer2MEGA65/star":{"post":"Z1ck_oiP68BzYdsJVjm5QStFY2Gx-TEXJ3JA3dzxcRfZQRol7x9ADgnelRcaT4K9gVhIlNu8j4OBZsZwkT46HQ"},"/sy2002/MiSTer2MEGA65/unstar":{"post":"qfJjEyJGCnInnAE9k2_PwI8phZtPYECSUedfWFYrwASe7pxwejcytxw_KhdQv_Gq9kkrN9Oi4wHN2zRuUksgbA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"os9krpDrF-qg3901kzuvxO6pHNrI_TG_OBDgqrgcbE___CwBspyrhpcEcaGvNyHgDgmgXVg-2Cv7rFWwGGG5-g"}}},"title":"Repository search results"}