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A good peach
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A good peach

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13 stars written in Verilog
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Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Verilog 2,606 1,006 Updated Mar 24, 2021
Verilog 1,188 250 Updated Sep 21, 2024

Verilog library for ASIC and FPGA designers

Verilog 1,156 284 Updated May 8, 2024

An open source GPU based off of the AMD Southern Islands ISA.

Verilog 1,036 236 Updated Sep 25, 2017

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

Verilog 997 77 Updated Dec 15, 2022

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Verilog 619 102 Updated Dec 21, 2023

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

Verilog 579 102 Updated Jan 3, 2020

synthesiseable ieee 754 floating point library in verilog

Verilog 515 142 Updated Mar 13, 2023

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

Verilog 255 64 Updated Jul 28, 2020

NES in Verilog

Verilog 185 60 Updated May 11, 2021

FPGA implementation of Cellular Neural Network (CNN)

Verilog 135 83 Updated Mar 30, 2018
Verilog 37 10 Updated Apr 4, 2021

An untyped lambda calculus machine designed in FPGA.

Verilog 14 1 Updated Sep 22, 2018