ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino

ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.

Python-based Hardware Design Processing Toolkit for Verilog HDL

A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.

SystemVerilog parser library fully compliant with IEEE 1800-2017

Icarus Verilog

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

SystemVerilog compiler and language services

NJU Virtual Board

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Reads a state transition system and performs property checking

A (concrete or symbolic) implementation of IEEE-754 / SMT-LIB floating-point

Bitwuzla is a Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, floating-point arithmetic, arrays and uninterpreted functions and their combinations. Its name …

Python API to Unified Coverage Interoperability Standard (UCIS) Data