rv64v: using (eew, emul) to generate vload's tail elements (OpenXiang…

…Shan#389)

* rv64v: using (eew, emul) to generate vload's tail elements

* rv64v: using int64 or uint64 variables for vload and vstore

src/isa/riscv64/instr/rvv/vldst_impl.c

@@ -142,9 +142,10 @@ static void index_vload_check(int mode, Decode *s) {
 void vld(int mode, int is_signed, Decode *s, int mmu_mode) {
   vload_check(mode, s);
   if(check_vstart_ignore(s)) return;
-  word_t idx;
-  uint64_t nf, fn, vl_val, base_addr, vd, addr;
-  int eew, emul, stride, is_unit_stride;
+  uint64_t idx;
+  uint64_t nf, fn, vl_val, base_addr, vd, addr, is_unit_stride;
+  int64_t stride;
+  int eew, emul, vemul;
 
   // s->v_width is the bytes of a unit
   // eew is the coding like vsew
@@ -159,6 +160,7 @@ void vld(int mode, int is_signed, Decode *s, int mmu_mode) {
   emul = vtype->vlmul > 4 ? vtype->vlmul - 8 + eew - vtype->vsew : vtype->vlmul + eew - vtype->vsew;
   isa_emul_check(mode == MODE_MASK ? 1 : emul, 1);
   emul = emul < 0 ? 0 : emul;
+  vemul = emul;
   emul = 1 << emul;
 
   if (mode == MODE_STRIDED) {
@@ -195,7 +197,7 @@ void vld(int mode, int is_signed, Decode *s, int mmu_mode) {
   }
 
   if (RVV_AGNOSTIC && (mode == MODE_MASK || vtype->vta)) {   // set tail of vector register to 1
-    int vlmax =  mode == MODE_MASK ? VLEN / 8 : get_vlen_max(vtype->vsew, vtype->vlmul, 0);
+    int vlmax =  mode == MODE_MASK ? VLEN / 8 : get_vlen_max(eew, vemul, 0);
     for(idx = vl_val; idx < vlmax; idx++) {
       tmp_reg[1] = (uint64_t) -1;
       for (fn = 0; fn < nf; fn++) {
@@ -215,7 +217,7 @@ void vldx(int mode, int is_signed, Decode *s, int mmu_mode) {
   //        7  ->  64         3  ->  64
   index_vload_check(mode, s);
   if(check_vstart_ignore(s)) return;
-  word_t idx;
+  uint64_t idx;
   uint64_t nf = s->v_nf + 1, fn, vl_val, base_addr, vd, index, addr;
   int eew, lmul, index_width, data_width;
 
@@ -284,9 +286,10 @@ void vldx(int mode, int is_signed, Decode *s, int mmu_mode) {
 void vst(int mode, Decode *s, int mmu_mode) {
   vstore_check(mode, s);
   if(check_vstart_ignore(s)) return;
-  word_t idx;
-  uint64_t nf, fn, vl_val, base_addr, vd, addr;
-  int eew, emul, stride, is_unit_stride;
+  uint64_t idx;
+  uint64_t nf, fn, vl_val, base_addr, vd, addr, is_unit_stride;
+  int64_t stride;
+  int eew, emul;
 
   eew = 0;
   switch(s->v_width) {
@@ -335,7 +338,7 @@ void vst(int mode, Decode *s, int mmu_mode) {
 void vstx(int mode, Decode *s, int mmu_mode) {
   index_vload_check(mode, s);
   if(check_vstart_ignore(s)) return;
-  word_t idx;
+  uint64_t idx;
   uint64_t nf = s->v_nf + 1, fn, vl_val, base_addr, vd, index, addr;
   int eew, lmul, index_width, data_width;
 
@@ -398,7 +401,7 @@ static void isa_whole_reg_check(uint64_t vd, uint64_t nfields) {
 }
 
 void vlr(int mode, int is_signed, Decode *s, int mmu_mode) {
-  word_t idx, vreg_idx, offset, pos;
+  uint64_t idx, vreg_idx, offset, pos;
   uint64_t len, base_addr, vd, addr, elt_per_reg, size;
   int eew;
 
@@ -452,7 +455,7 @@ void vlr(int mode, int is_signed, Decode *s, int mmu_mode) {
 }
 
 void vsr(int mode, Decode *s, int mmu_mode) {
-  word_t idx, vreg_idx, offset, pos;
+  uint64_t idx, vreg_idx, offset, pos;
   uint64_t len, base_addr, vd, addr, elt_per_reg, size;
 
   // previous decode does not load vals for us