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Commits on Dec 28, 2020

• Merge pull request #158 from abejgonzalez/ibuf-low-power-constraint

  erikdanie

  committedDec 28, 2020
  f9fb9fd

Commits on Nov 15, 2020

• bump sifive-blocks (#157)

  

  Connor Lee

  committedNov 15, 2020
  337aa50

Commits on Nov 11, 2020

• Add utility function for IBUF_LOW_POWER

  abejgonzalez

  committedNov 11, 2020
  fcfadb4

Commits on Oct 29, 2020

• do not use deprecated stripBits parameter of TLToAXI4 (#156)

  hcook

  committedOct 29, 2020
  11055ec

Commits on Oct 19, 2020

• Merge pull request #155 from abejgonzalez/add-xilinx-drv-str

  erikdanie

  committedOct 19, 2020
  89a5efe

Commits on Oct 18, 2020

• Add Xilinx drive strength property

  abejgonzalez

  committedOct 18, 2020
  c877368

Commits on Sep 19, 2020

• Merge pull request #153 from sifive/Add_PorGen_overlay

  KowshikSiFive

  committedSep 19, 2020
  7379ca6

• Update wit-manifest to point to latest sifive-blocks

  KowshikSiFive

  committedSep 19, 2020
  5cbe297

Commits on Sep 17, 2020

• Merge pull request #152 from sifive/PMOD2_and_PCIeKey_on_VCU118NewShell

  Jacka1201

  committedSep 17, 2020
  dc1ebef

Commits on Sep 16, 2020

• Add PorGen Overlay

  KowshikSiFive

  committedSep 16, 2020
  cddc0de

• Keep PCIeOverlayKey in design

  

  Jacka Tsai

  committedSep 16, 2020
  1952e2c

Commits on Sep 14, 2020

• 1. Adding class "WithVCU118ShellPMOD2" to assign JTAG pinouts on J53 on VCU118

  

  Jacka Tsai

  committedSep 14, 2020
  06a5f1b

Commits on Sep 13, 2020

• Update PorGen

  KowshikSiFive

  committedSep 13, 2020
  396c958

Commits on Sep 10, 2020

• Fix JTAG Pin location on VCU118 J53

  

  Jacka Tsai

  committedSep 10, 2020
  b5b3709

• Add PCIeEdgeOverLaykey and PCIeFMCOverlayKey into PCIeOverlay.scala

  

  Jacka Tsai

  committedSep 10, 2020
  2e56ff7

• Add JTAG location and constraints on J53

  

  Jacka Tsai

  committedSep 10, 2020
  632d02d

Commits on Aug 27, 2020

• Merge pull request #150 from sifive/arty-led-fix-master

  erikdanie

  committedAug 27, 2020
  e8e7f8a

• fix arty LEDs

  erikdanie

  committedAug 27, 2020
  9e9b149

• SPIOverlay: Fix makeSink'd scope to sinkScope (#149)

  rmac-sifive

  committedAug 27, 2020
  dacb742

Commits on Aug 25, 2020

• SDIO Overlay: Refactor to be more useful for generic SPI IO creation (#148)

  rmac-sifive

  committedAug 25, 2020
  2d0747d

Commits on Aug 18, 2020

• Merge pull request #145 from sifive/sequencer-patch-1

  sequencer

  committedAug 18, 2020
  754a4cb

Commits on Aug 17, 2020

• add clock divider support

  sequencer

  committedAug 17, 2020
  ac1cbab

Commits on Aug 11, 2020

• Merge pull request #144 from sifive/fix-tcl-if

  erikdanie

  committedAug 11, 2020
  a913cfa

• refactor tcl code that wasn't executing correctly

  erikdanie

  committedAug 11, 2020
  d4b3878

• Merge pull request #142 from sifive/add-ci

  terpstra

  committedAug 11, 2020
  8de0b7b

• CI: add a scala compilation check

  terpstra

  committedAug 11, 2020
  4d2a19d

• wit-manifest: bump for newest api-generator-sifive

  terpstra

  committedAug 11, 2020
  a6317fb

• wit-manifest: bump sifive-blocks to newest version

  terpstra

  committedAug 11, 2020
  5e5e4a3

Commits on Aug 10, 2020

• wit-manifest: remove dependency on firrtl+chisel+api-scala-sifive

  terpstra

  committedAug 10, 2020
  fabd952

• wit-manifest: depend on current rocket-chip

  terpstra

  committedAug 10, 2020
  cff7aed

Commits on Aug 4, 2020

• Merge pull request #140 from sequencer/bscan_fix_again

  sequencer

  committedAug 4, 2020
  09e7b20

Commits on Jul 28, 2020

• add vcu118 bscan.

  sequencer

  committedJul 28, 2020
  b08c49b

• fix bscan again

  sequencer

  committedJul 28, 2020
  8f49099

Commits on Jul 27, 2020

• SDIO: chisel3 <> can't decide connection direction (#141)

  terpstra

  committedJul 27, 2020
  068aea5

Commits on Jul 22, 2020

• xdma: support BARs with physical address != PCIe address (#139)

  terpstra

  committedJul 22, 2020
  6473516

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