A minimal GPU design in Verilog to learn how GPUs work from the ground up

Send video/audio over HDMI on an FPGA

RSD: RISC-V Out-of-Order Superscalar Processor

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

VeeR EH1 core

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

BaseJump STL: A Standard Template Library for SystemVerilog

NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards

Network on Chip Implementation written in SytemVerilog

Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software …

IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

Proposed RISC-V Composable Custom Extensions Specification

Featherweight RISC-V implementation

Stratix V PCIe Ledblink (for usage in Microsoft Storey Peak boards)

Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.

Demo: how to create a custom EBRICK

Analog Circuit Simulator

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.