CoreAmstrad source code
This core was refactored into Xilinx NEXYS4 dev platform, and then translated finally into MiST-board final platform (Altera)
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vhd : vhdl files
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v : verilog files (MiST-board controllers, added in main quartus schematic)
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qpf : quartus project (FGPAmstrad.qpf)
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bdf : quartus visual schematic (FGPAmstrad_MiST_top.bdf)
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bsf : quartus visual component
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sdc : quartus time constraints (FPGAmstrad_MiST_top.sdc)
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qsf : quartus port mapping (FPGAmstrad_MiST_top.qsf)
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xise : Xilinx webpack project (BuildYourOwnZ80Computer.xise/gise)
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sch : Xilinx webpack visual schematic
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sym : Xilinx webpack visual component
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ucf : Xilinx webpack time constraints and port mapping (Nexys4_Master.ucf)
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vhf : vhd file generated from sch file
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FPGAmstrad_amstrad_motherboard : amstrad_motherboard.sch Xilinx schematic converted into a vhf/vhd/bsf Quartus component
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FPGAmstrad_amstrad_video : amstrad_video.sch Xilinx schematic converted into a vhf/vhd/bsf Quartus component
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FPGAmstrad_bootloader_sd : bootloader_sd.sch Xilinx schematic converted into a vhf/vhd/bsf Quartus component
MIST_* MiST glue code (added in main quartus schematic)
Flow Status Successful - Tue Aug 11 06:03:56 2015 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name FGPAmstrad_MiST_top Top-level Entity Name FGPAmstrad_MiST_top Family Cyclone III Device EP3C25E144C8 Timing Models Final Total logic elements 13,933 / 24,624 ( 57 % ) Total combinational functions 13,110 / 24,624 ( 53 % ) Dedicated logic registers 4,775 / 24,624 ( 19 % ) Total registers 4791 Total pins 70 / 83 ( 84 % ) Total virtual pins 0 Total memory bits 532,496 / 608,256 ( 88 % ) Embedded Multiplier 9-bit elements 30 / 132 ( 23 % ) Total PLLs 1 / 4 ( 25 % )