rv64v: fix vlmax calculate and align check for vlm instruction (OpenX…

…iangShan#256) * rv64v: fix vlmax compute for vlm instruction * rv64v: fix align check for vlm/vsm
phaseworld · Jan 26, 2024 · 7a5b3d0 · 7a5b3d0
1 parent af27052
commit 7a5b3d0
Showing 1 changed file with 8 additions and 8 deletions.
diff --git a/src/isa/riscv64/instr/rvv/vldst_impl.c b/src/isa/riscv64/instr/rvv/vldst_impl.c
@@ -57,7 +57,7 @@ void vld(int mode, int is_signed, Decode *s, int mmu_mode) {
     default: break;
   }
   emul = vtype->vlmul > 4 ? vtype->vlmul - 8 + eew - vtype->vsew : vtype->vlmul + eew - vtype->vsew;
-  isa_emul_check(emul, 1);
+  isa_emul_check(mode == MODE_MASK ? 1 : emul, 1);
   emul = emul < 0 ? 0 : emul;
   emul = 1 << emul;
 
@@ -82,24 +82,24 @@ void vld(int mode, int is_signed, Decode *s, int mmu_mode) {
       if (RVV_AGNOSTIC && vtype->vma) {
         tmp_reg[1] = (uint64_t) -1;
         for (fn = 0; fn < nf; fn++) {
-          set_vreg(vd + fn * emul, idx, tmp_reg[1], eew, vtype->vlmul, 1);
+          set_vreg(vd + fn * emul, idx, tmp_reg[1], eew, vtype->vlmul, mode == MODE_MASK ? 0 : 1);
         }
       }
       continue;
     }
     for (fn = 0; fn < nf; fn++) {
       addr = base_addr + idx * stride + (idx * nf * is_stride + fn) * s->v_width;
       rtl_lm(s, &tmp_reg[1], &addr, 0, s->v_width, mmu_mode);
-      set_vreg(vd + fn * emul, idx, tmp_reg[1], eew, vtype->vlmul, 1);
+      set_vreg(vd + fn * emul, idx, tmp_reg[1], eew, vtype->vlmul, mode == MODE_MASK ? 0 : 1);
     }
   }
 
-  if (RVV_AGNOSTIC && vtype->vta) {   // set tail of vector register to 1
-    int vlmax = get_vlen_max(eew, vtype->vlmul, 0);
+  if (RVV_AGNOSTIC && (mode == MODE_MASK || vtype->vta)) {   // set tail of vector register to 1
+    int vlmax = mode == MODE_MASK ? VLEN / 8 : get_vlen_max(eew, vtype->vlmul, 0);
     for(idx = vl_val; idx < vlmax; idx++) {
       tmp_reg[1] = (uint64_t) -1;
       for (fn = 0; fn < nf; fn++) {
-        set_vreg(vd + fn * emul, idx, tmp_reg[1], eew, vtype->vlmul, 1);
+        set_vreg(vd + fn * emul, idx, tmp_reg[1], eew, vtype->vlmul, mode == MODE_MASK ? 0 : 1);
       }
     }
   }
@@ -203,7 +203,7 @@ void vst(int mode, Decode *s, int mmu_mode) {
     default: break;
   }
   emul = vtype->vlmul > 4 ? vtype->vlmul - 8 + eew - vtype->vsew : vtype->vlmul + eew - vtype->vsew;
-  isa_emul_check(emul, 1);
+  isa_emul_check(mode == MODE_MASK ? 1 : emul, 1);
   emul = emul < 0 ? 0 : emul;
   emul = 1 << emul;
 
@@ -228,7 +228,7 @@ void vst(int mode, Decode *s, int mmu_mode) {
       continue;
     }
     for (fn = 0; fn < nf; fn++) {
-      get_vreg(vd + fn * emul, idx, &tmp_reg[1], eew, vtype->vlmul, 0, 1);
+      get_vreg(vd + fn * emul, idx, &tmp_reg[1], eew, vtype->vlmul, 0, mode == MODE_MASK ? 0 : 1);
       addr = base_addr + idx * stride + (idx * nf * is_stride + fn) * s->v_width;
       rtl_sm(s, &tmp_reg[1], &addr, 0, s->v_width, mmu_mode);
     }