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[Arc] Infer StateOp reset from CompReg #4997

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merged 10 commits into from
Apr 14, 2023
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Return on multiple reset error
Co-authored-by: Martin Erhart <maerhart@outlook.com>
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TaoBi22 and maerhart committed Apr 12, 2023
commit 2197394cf2362fe23a9d087f5feba53fd2949719
5 changes: 2 additions & 3 deletions lib/Conversion/ConvertToArcs/ConvertToArcs.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -322,10 +322,9 @@ LogicalResult Converter::absorbRegs(HWModuleOp module) {
arc.setLatency(arc.getLatency() + 1);
if (reset) {
if (arc.getReset())
arc.emitError("StateOp tried to infer reset from CompReg, but already "
return arc.emitError("StateOp tried to infer reset from CompReg, but already "
"had a reset.");
else
arc.getResetMutable().assign(reset);
arc.getResetMutable().assign(reset);
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What if there is already a reset present?

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Are you happy for this just to be covered with an assertion? I suppose we could comb.or multiple reset lines, but I'm unable to think of a situation where you would expect/desire a reset to already be present on the StateOp at this point, unless there are additions you have planned.

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The situation/assertion could be triggered with an input that has both state ops and compreg ops in there which does not happen currently. But the fact that a user can construct such an IR is enough of a reason that we shouldn't use an assertion. However, I think it's not necessary to support this case right now, so I would just go for an emitError in that case as well.

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Ah of course! Sounds good, I'll do that :)

}
if (llvm::any_of(absorbedNames, [](auto name) {
return !name.template cast<StringAttr>().getValue().empty();
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