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[Arc] Infer StateOp reset from CompReg #4997

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merged 10 commits into from
Apr 14, 2023
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TaoBi22
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@TaoBi22 TaoBi22 commented Apr 11, 2023

Update the ConvertToArcs pass so that if a CompReg has an explicit reset operand, this becomes the StateOp's reset operand. Since StateOps currently can only reset to 0, the pass fails if any CompReg's reset value is not a constant 0.

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Thanks for fixing this! The code looks good to me. Could you maybe add some regression tests for the new behavior (covering both the trivial and non-trivial cases)?

arc.getClockMutable().assign(clock);
arc.setLatency(arc.getLatency() + 1);
if (reset)
arc.getResetMutable().assign(reset);
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What if there is already a reset present?

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Are you happy for this just to be covered with an assertion? I suppose we could comb.or multiple reset lines, but I'm unable to think of a situation where you would expect/desire a reset to already be present on the StateOp at this point, unless there are additions you have planned.

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The situation/assertion could be triggered with an input that has both state ops and compreg ops in there which does not happen currently. But the fact that a user can construct such an IR is enough of a reason that we shouldn't use an assertion. However, I think it's not necessary to support this case right now, so I would just go for an emitError in that case as well.

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Ah of course! Sounds good, I'll do that :)

@maerhart maerhart added the Arc Involving the `arc` dialect label Apr 11, 2023
@TaoBi22 TaoBi22 requested a review from maerhart April 12, 2023 16:20
lib/Conversion/ConvertToArcs/ConvertToArcs.cpp Outdated Show resolved Hide resolved
Comment on lines +397 to +401
builder.create<StateOp>(loc, defOp, std::get<0>(clockAndResetAndOp),
/*enable=*/Value{}, 1, inputs);
auto reset = std::get<1>(clockAndResetAndOp);
if (reset)
arcOp.getResetMutable().assign(reset);
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Good catch it was actually passed as the enable here! Might be worth adding another builder to ArcOps.td for this case.

@@ -0,0 +1,30 @@
// RUN: arcilator %s --inline=0 --until-before=state-lowering | FileCheck %s
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I'm wondering why this is added as an integration test. Couldn't we just add it do the existing regression tests for ConvertToArcs?

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Agreed! Will fix

// CHECK-DAG: arc.output [[ARG0]]
// CHECK-NEXT: }

// CHECK-DAG: hw.module @Trivial([[CLOCK:%.+]]: i1, [[I0:%.+]]: i4, [[RESET:%.+]]: i1)
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I think it'd be better to use CHECK-LABEL here and in general only use CHECK-DAG where it really makes sense/is necessary.

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I've hopefully addressed this now, but I'm not particularly well acquainted with FileCheck & its preferred usage so feedback is appreciated!

Comment on lines 20 to 21
// CHECK-DAG: [[RES2:%.+]] = arc.state @[[ARC]]([[I0_2]]) clock [[CLOCK]] reset [[RESET1]] lat 1 {names = ["foo"]
// CHECK-DAG: [[RES3:%.+]] = arc.state @[[ARC]]([[I0_2]]) clock [[CLOCK]] reset [[RESET2]] lat 1 {names = ["bar"]
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For example, I think here it's fine to use CHECK-DAG, but not strictly necessary.

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LGTM! Thanks for all the adjustments!

@maerhart maerhart merged commit a264460 into llvm:main Apr 14, 2023
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2 participants