CSR: fix tval for breakpoint exception & bump ready-to-run

husipeng24 · Apr 11, 2024 · bee4a1c · bee4a1c
1 parent 3b02df1
commit bee4a1c
Show file tree

Hide file tree

Showing 2 changed files with 6 additions and 1 deletion.
diff --git a/ready-to-run b/ready-to-run
diff --git a/src/isa/riscv64/system/intr.c b/src/isa/riscv64/system/intr.c
@@ -115,6 +115,8 @@ word_t raise_intr(word_t NO, vaddr_t epc) {
       case EX_LAM: case EX_SAM:
       case EX_IAF: case EX_LAF: case EX_SAF:
         break;
+      case EX_BP : vstval->val = epc;
+        break;
       default: vstval->val = 0;
     }
     cpu.v = 1;
@@ -152,6 +154,8 @@ word_t raise_intr(word_t NO, vaddr_t epc) {
 #ifdef CONFIG_TVAL_EX_II
       case EX_II: stval->val = cpu.instr; break;
 #endif
+      case EX_BP : 
+        stval->val = epc; break;
       default: stval->val = 0;
 #ifdef CONFIG_RVH
                htval->val = 0;
@@ -187,6 +191,7 @@ word_t raise_intr(word_t NO, vaddr_t epc) {
 #ifdef CONFIG_TVAL_EX_II
       case EX_II: mtval->val = cpu.instr; break;
 #endif
+      case EX_BP : mtval->val = epc; break;
       default: mtval->val = 0;
 #ifdef CONFIG_RVH
                mtval2->val = 0;