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half-adder, full-adder
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FuadAlAbir committed Feb 3, 2020
1 parent b1fa518 commit e81244c
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8 changes: 8 additions & 0 deletions Project 1/full_adder/circuit.v
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module full_adder (A, B, Cin, S, Cout);
input A, B, Cin;
output S, Cout;

assign S = A^B^Cin;
assign Cout = A&B | Cin&(A^B);

endmodule
106 changes: 106 additions & 0 deletions Project 1/full_adder/sim
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#! /usr/bin/vvp
:ivl_version "10.1 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "system";
:vpi_module "vhdl_sys";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0x55c7d247d4d0 .scope module, "testbench" "testbench" 2 1;
.timescale 0 0;
v0x55c7d249de80_0 .var "A", 0 0;
v0x55c7d249df40_0 .var "B", 0 0;
v0x55c7d249dfe0_0 .var "Cin", 0 0;
v0x55c7d249e0e0_0 .net "Cout", 0 0, L_0x55c7d249e700; 1 drivers
v0x55c7d249e1b0_0 .net "S", 0 0, L_0x55c7d249e390; 1 drivers
S_0x55c7d247d650 .scope module, "DUT" "full_adder" 2 4, 3 1 0, S_0x55c7d247d4d0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A"
.port_info 1 /INPUT 1 "B"
.port_info 2 /INPUT 1 "Cin"
.port_info 3 /OUTPUT 1 "S"
.port_info 4 /OUTPUT 1 "Cout"
L_0x55c7d249e250 .functor XOR 1, v0x55c7d249de80_0, v0x55c7d249df40_0, C4<0>, C4<0>;
L_0x55c7d249e390 .functor XOR 1, L_0x55c7d249e250, v0x55c7d249dfe0_0, C4<0>, C4<0>;
L_0x55c7d249e4f0 .functor AND 1, v0x55c7d249de80_0, v0x55c7d249df40_0, C4<1>, C4<1>;
L_0x55c7d249e560 .functor XOR 1, v0x55c7d249de80_0, v0x55c7d249df40_0, C4<0>, C4<0>;
L_0x55c7d249e690 .functor AND 1, v0x55c7d249dfe0_0, L_0x55c7d249e560, C4<1>, C4<1>;
L_0x55c7d249e700 .functor OR 1, L_0x55c7d249e4f0, L_0x55c7d249e690, C4<0>, C4<0>;
v0x55c7d247d850_0 .net "A", 0 0, v0x55c7d249de80_0; 1 drivers
v0x55c7d249d730_0 .net "B", 0 0, v0x55c7d249df40_0; 1 drivers
v0x55c7d249d7f0_0 .net "Cin", 0 0, v0x55c7d249dfe0_0; 1 drivers
v0x55c7d249d890_0 .net "Cout", 0 0, L_0x55c7d249e700; alias, 1 drivers
v0x55c7d249d950_0 .net "S", 0 0, L_0x55c7d249e390; alias, 1 drivers
v0x55c7d249da60_0 .net *"_s0", 0 0, L_0x55c7d249e250; 1 drivers
v0x55c7d249db40_0 .net *"_s4", 0 0, L_0x55c7d249e4f0; 1 drivers
v0x55c7d249dc20_0 .net *"_s6", 0 0, L_0x55c7d249e560; 1 drivers
v0x55c7d249dd00_0 .net *"_s8", 0 0, L_0x55c7d249e690; 1 drivers
.scope S_0x55c7d247d4d0;
T_0 ;
%vpi_call 2 8 "$monitor", $time, " A=%b, B=%b, Cin=%b, S=%b, Cout=%b", v0x55c7d249de80_0, v0x55c7d249df40_0, v0x55c7d249dfe0_0, v0x55c7d249e1b0_0, v0x55c7d249e0e0_0 {0 0 0};
%delay 5, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c7d249de80_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c7d249df40_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c7d249dfe0_0, 0, 1;
%delay 5, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c7d249de80_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c7d249df40_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55c7d249dfe0_0, 0, 1;
%delay 5, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c7d249de80_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55c7d249df40_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c7d249dfe0_0, 0, 1;
%delay 5, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c7d249de80_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55c7d249df40_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55c7d249dfe0_0, 0, 1;
%delay 5, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55c7d249de80_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c7d249df40_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c7d249dfe0_0, 0, 1;
%delay 5, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55c7d249de80_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c7d249df40_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55c7d249dfe0_0, 0, 1;
%delay 5, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55c7d249de80_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55c7d249df40_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c7d249dfe0_0, 0, 1;
%delay 5, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55c7d249de80_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55c7d249df40_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55c7d249dfe0_0, 0, 1;
%delay 5, 0;
%vpi_call 2 17 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"tb.v";
"circuit.v";
19 changes: 19 additions & 0 deletions Project 1/full_adder/tb.v
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module testbench;
reg A, B, Cin;
wire S, Cout;
full_adder DUT(A, B, Cin, S, Cout);

initial
begin
$monitor ($time, " A=%b, B=%b, Cin=%b, S=%b, Cout=%b", A, B, Cin, S, Cout);
#5 A=0; B=0; Cin=0;
#5 A=0; B=0; Cin=1;
#5 A=0; B=1; Cin=0;
#5 A=0; B=1; Cin=1;
#5 A=1; B=0; Cin=0;
#5 A=1; B=0; Cin=1;
#5 A=1; B=1; Cin=0;
#5 A=1; B=1; Cin=1;
#5 $finish;
end
endmodule
11 changes: 11 additions & 0 deletions Project 1/half_adder/circuit.v
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module half_adder (A, B, S, C);
input A, B;
output S, C;

assign #1 S = A^B;
assign #1 C = A&B;

// xor #1 G1 (S, A, B);
// and #1 G2 (C, A, B);

endmodule
55 changes: 55 additions & 0 deletions Project 1/half_adder/sim
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#! /usr/bin/vvp
:ivl_version "10.1 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "system";
:vpi_module "vhdl_sys";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0x55e005739730 .scope module, "testbench" "testbench" 2 1;
.timescale 0 0;
v0x55e005759c90_0 .var "A", 0 0;
v0x55e005759d50_0 .var "B", 0 0;
v0x55e005759e20_0 .net "C", 0 0, L_0x55e00575a1f0; 1 drivers
v0x55e005759f20_0 .net "S", 0 0, L_0x55e005759ff0; 1 drivers
S_0x55e0057398b0 .scope module, "DUT" "half_adder" 2 4, 3 1 0, S_0x55e005739730;
.timescale 0 0;
.port_info 0 /INPUT 1 "A"
.port_info 1 /INPUT 1 "B"
.port_info 2 /OUTPUT 1 "S"
.port_info 3 /OUTPUT 1 "C"
L_0x55e005759ff0/d .functor XOR 1, v0x55e005759c90_0, v0x55e005759d50_0, C4<0>, C4<0>;
L_0x55e005759ff0 .delay 1 (1,1,1) L_0x55e005759ff0/d;
L_0x55e00575a1f0/d .functor AND 1, v0x55e005759c90_0, v0x55e005759d50_0, C4<1>, C4<1>;
L_0x55e00575a1f0 .delay 1 (1,1,1) L_0x55e00575a1f0/d;
v0x55e005739aa0_0 .net "A", 0 0, v0x55e005759c90_0; 1 drivers
v0x55e0057599c0_0 .net "B", 0 0, v0x55e005759d50_0; 1 drivers
v0x55e005759a80_0 .net "C", 0 0, L_0x55e00575a1f0; alias, 1 drivers
v0x55e005759b20_0 .net "S", 0 0, L_0x55e005759ff0; alias, 1 drivers
.scope S_0x55e005739730;
T_0 ;
%vpi_call 2 8 "$monitor", $time, " A=%b, B=%b, C=%b, S=%b", v0x55e005759c90_0, v0x55e005759d50_0, v0x55e005759e20_0, v0x55e005759f20_0 {0 0 0};
%delay 5, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55e005759c90_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55e005759d50_0, 0, 1;
%delay 5, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55e005759c90_0, 0, 1;
%delay 5, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55e005759d50_0, 0, 1;
%delay 5, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55e005759c90_0, 0, 1;
%delay 5, 0;
%vpi_call 2 13 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"tb.v";
"circuit.v";
15 changes: 15 additions & 0 deletions Project 1/half_adder/tb.v
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@@ -0,0 +1,15 @@
module testbench;
reg A, B;
wire S, C;
half_adder DUT(A, B, S, C);

initial
begin
$monitor ($time, " A=%b, B=%b, C=%b, S=%b", A, B, C, S);
#5 A=0; B=0;
#5 A=1;
#5 B=1;
#5 A=0;
#5 $finish;
end
endmodule
86 changes: 43 additions & 43 deletions Project 1/zeroth_circuit/sim
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Expand Up @@ -6,16 +6,16 @@
:vpi_module "vhdl_sys";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0x556aaba85c30 .scope module, "testbench" "testbench" 2 1;
S_0x55d57ea13c30 .scope module, "testbench" "testbench" 2 1;
.timescale 0 0;
v0x556aabaa6620_0 .var "A", 0 0;
v0x556aabaa66e0_0 .var "B", 0 0;
v0x556aabaa67b0_0 .var "C", 0 0;
v0x556aabaa68b0_0 .var "D", 0 0;
v0x556aabaa6980_0 .var "E", 0 0;
v0x556aabaa6a20_0 .var "F", 0 0;
v0x556aabaa6af0_0 .net "Y", 0 0, L_0x556aabaa71f0; 1 drivers
S_0x556aaba85db0 .scope module, "DUT" "first_circuit" 2 4, 3 1 0, S_0x556aaba85c30;
v0x55d57ea34620_0 .var "A", 0 0;
v0x55d57ea346e0_0 .var "B", 0 0;
v0x55d57ea347b0_0 .var "C", 0 0;
v0x55d57ea348b0_0 .var "D", 0 0;
v0x55d57ea34980_0 .var "E", 0 0;
v0x55d57ea34a20_0 .var "F", 0 0;
v0x55d57ea34af0_0 .net "Y", 0 0, L_0x55d57ea351f0; 1 drivers
S_0x55d57ea13db0 .scope module, "DUT" "first_circuit" 2 4, 3 1 0, S_0x55d57ea13c30;
.timescale 0 0;
.port_info 0 /INPUT 1 "A"
.port_info 1 /INPUT 1 "B"
Expand All @@ -24,57 +24,57 @@ S_0x556aaba85db0 .scope module, "DUT" "first_circuit" 2 4, 3 1 0, S_0x556aaba85c
.port_info 4 /INPUT 1 "E"
.port_info 5 /INPUT 1 "F"
.port_info 6 /OUTPUT 1 "Y"
L_0x556aabaa6bc0/d .functor NAND 1, v0x556aabaa6620_0, v0x556aabaa66e0_0, C4<1>, C4<1>;
L_0x556aabaa6bc0 .delay 1 (1,1,1) L_0x556aabaa6bc0/d;
L_0x556aabaa6da0/d .functor AND 1, v0x556aabaa67b0_0, L_0x556aabaa6f50, v0x556aabaa68b0_0, C4<1>;
L_0x556aabaa6da0 .delay 1 (2,2,2) L_0x556aabaa6da0/d;
L_0x556aabaa6f50 .functor NOT 1, v0x556aabaa66e0_0, C4<0>, C4<0>, C4<0>;
L_0x556aabaa7010/d .functor NOR 1, v0x556aabaa6980_0, v0x556aabaa6a20_0, C4<0>, C4<0>;
L_0x556aabaa7010 .delay 1 (1,1,1) L_0x556aabaa7010/d;
L_0x556aabaa71f0/d .functor NAND 1, L_0x556aabaa6bc0, L_0x556aabaa6da0, L_0x556aabaa7010, C4<1>;
L_0x556aabaa71f0 .delay 1 (1,1,1) L_0x556aabaa71f0/d;
v0x556aaba86030_0 .net "A", 0 0, v0x556aabaa6620_0; 1 drivers
v0x556aabaa5d70_0 .net "B", 0 0, v0x556aabaa66e0_0; 1 drivers
v0x556aabaa5e30_0 .net "C", 0 0, v0x556aabaa67b0_0; 1 drivers
v0x556aabaa5ed0_0 .net "D", 0 0, v0x556aabaa68b0_0; 1 drivers
v0x556aabaa5f90_0 .net "E", 0 0, v0x556aabaa6980_0; 1 drivers
v0x556aabaa60a0_0 .net "F", 0 0, v0x556aabaa6a20_0; 1 drivers
v0x556aabaa6160_0 .net "Y", 0 0, L_0x556aabaa71f0; alias, 1 drivers
v0x556aabaa6220_0 .net *"_s0", 0 0, L_0x556aabaa6f50; 1 drivers
v0x556aabaa6300_0 .net "t1", 0 0, L_0x556aabaa6bc0; 1 drivers
v0x556aabaa63c0_0 .net "t2", 0 0, L_0x556aabaa6da0; 1 drivers
v0x556aabaa6480_0 .net "t3", 0 0, L_0x556aabaa7010; 1 drivers
.scope S_0x556aaba85c30;
L_0x55d57ea34bc0/d .functor NAND 1, v0x55d57ea34620_0, v0x55d57ea346e0_0, C4<1>, C4<1>;
L_0x55d57ea34bc0 .delay 1 (1,1,1) L_0x55d57ea34bc0/d;
L_0x55d57ea34da0/d .functor AND 1, v0x55d57ea347b0_0, L_0x55d57ea34f50, v0x55d57ea348b0_0, C4<1>;
L_0x55d57ea34da0 .delay 1 (2,2,2) L_0x55d57ea34da0/d;
L_0x55d57ea34f50 .functor NOT 1, v0x55d57ea346e0_0, C4<0>, C4<0>, C4<0>;
L_0x55d57ea35010/d .functor NOR 1, v0x55d57ea34980_0, v0x55d57ea34a20_0, C4<0>, C4<0>;
L_0x55d57ea35010 .delay 1 (1,1,1) L_0x55d57ea35010/d;
L_0x55d57ea351f0/d .functor NAND 1, L_0x55d57ea34bc0, L_0x55d57ea34da0, L_0x55d57ea35010, C4<1>;
L_0x55d57ea351f0 .delay 1 (1,1,1) L_0x55d57ea351f0/d;
v0x55d57ea14030_0 .net "A", 0 0, v0x55d57ea34620_0; 1 drivers
v0x55d57ea33d70_0 .net "B", 0 0, v0x55d57ea346e0_0; 1 drivers
v0x55d57ea33e30_0 .net "C", 0 0, v0x55d57ea347b0_0; 1 drivers
v0x55d57ea33ed0_0 .net "D", 0 0, v0x55d57ea348b0_0; 1 drivers
v0x55d57ea33f90_0 .net "E", 0 0, v0x55d57ea34980_0; 1 drivers
v0x55d57ea340a0_0 .net "F", 0 0, v0x55d57ea34a20_0; 1 drivers
v0x55d57ea34160_0 .net "Y", 0 0, L_0x55d57ea351f0; alias, 1 drivers
v0x55d57ea34220_0 .net *"_s0", 0 0, L_0x55d57ea34f50; 1 drivers
v0x55d57ea34300_0 .net "t1", 0 0, L_0x55d57ea34bc0; 1 drivers
v0x55d57ea343c0_0 .net "t2", 0 0, L_0x55d57ea34da0; 1 drivers
v0x55d57ea34480_0 .net "t3", 0 0, L_0x55d57ea35010; 1 drivers
.scope S_0x55d57ea13c30;
T_0 ;
%vpi_call 2 8 "$dumpfile", "wave.vcd" {0 0 0};
%vpi_call 2 9 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x556aaba85c30 {0 0 0};
%vpi_call 2 10 "$monitor", $time, " A=%b, B=%b, C=%b, D=%b, E=%b, F=%b, Y=%b ", v0x556aabaa6620_0, v0x556aabaa66e0_0, v0x556aabaa67b0_0, v0x556aabaa68b0_0, v0x556aabaa6980_0, v0x556aabaa6a20_0, v0x556aabaa6af0_0 {0 0 0};
%vpi_call 2 9 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x55d57ea13c30 {0 0 0};
%vpi_call 2 10 "$monitor", $time, " A=%b, B=%b, C=%b, D=%b, E=%b, F=%b, Y=%b ", v0x55d57ea34620_0, v0x55d57ea346e0_0, v0x55d57ea347b0_0, v0x55d57ea348b0_0, v0x55d57ea34980_0, v0x55d57ea34a20_0, v0x55d57ea34af0_0 {0 0 0};
%delay 5, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x556aabaa6620_0, 0, 1;
%store/vec4 v0x55d57ea34620_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x556aabaa66e0_0, 0, 1;
%store/vec4 v0x55d57ea346e0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x556aabaa67b0_0, 0, 1;
%store/vec4 v0x55d57ea347b0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x556aabaa68b0_0, 0, 1;
%store/vec4 v0x55d57ea348b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x556aabaa6980_0, 0, 1;
%store/vec4 v0x55d57ea34980_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x556aabaa6a20_0, 0, 1;
%store/vec4 v0x55d57ea34a20_0, 0, 1;
%delay 5, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x556aabaa6620_0, 0, 1;
%store/vec4 v0x55d57ea34620_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x556aabaa67b0_0, 0, 1;
%store/vec4 v0x55d57ea347b0_0, 0, 1;
%delay 5, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x556aabaa6620_0, 0, 1;
%store/vec4 v0x55d57ea34620_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x556aabaa67b0_0, 0, 1;
%store/vec4 v0x55d57ea347b0_0, 0, 1;
%delay 5, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x556aabaa6a20_0, 0, 1;
%store/vec4 v0x55d57ea34a20_0, 0, 1;
%delay 5, 0;
%vpi_call 2 15 "$finish" {0 0 0};
%end;
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2 changes: 1 addition & 1 deletion Project 1/zeroth_circuit/wave.vcd
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
$date
Thu Jan 30 08:04:04 2020
Mon Feb 3 18:02:20 2020
$end
$version
Icarus Verilog
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