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Commits on Apr 22, 2024

• test on zynq

  chaozhang2000

  committedApr 22, 2024
  56da451

Commits on Apr 15, 2024

• support mul pes access one mem

  chaozhang2000

  committedApr 15, 2024
  2626ce9

Commits on Apr 14, 2024

• fix finish signal bug

  chaozhang2000

  committedApr 14, 2024
  a850711

• fix bugs, can run conv3 demo

  chaozhang2000

  committedApr 14, 2024
  4961953

• fix a bug,modify instmem constmem shiftconstmem waddr

  chaozhang2000

  committedApr 14, 2024
  1c2d00b

Commits on Apr 13, 2024

• first finish and ready to config cgra with true bitstream

  chaozhang2000

  committedApr 13, 2024
  5662784

• add axi-streamm to read date from datamem

  chaozhang2000

  committedApr 13, 2024
  5f0221a

Commits on Apr 12, 2024

• add axi-stream load data to datamem

  chaozhang2000

  committedApr 12, 2024
  8b534b5

Commits on Apr 11, 2024

• first finish config

  chaozhang2000

  committedApr 11, 2024
  dfb6087

Commits on Apr 9, 2024

• first add AXI-Stream to CGRA

  chaozhang2000

  committedApr 9, 2024
  d82a94d

Commits on Apr 8, 2024

• add AXI-Lite in utils

  chaozhang2000

  committedApr 8, 2024
  a1e88fa

Commits on Apr 7, 2024

• temp save

  chaozhang2000

  committedApr 7, 2024
  5c4246c

Commits on Mar 29, 2024

• add Link

  chaozhang2000

  committedMar 29, 2024
  6188110

• add load and store in fu

  chaozhang2000

  committedMar 29, 2024
  cf99be9

Commits on Mar 28, 2024

• start rm valid

  chaozhang2000

  committedMar 28, 2024
  1c613f3

Commits on Mar 15, 2024

• add canupdatestate signal

  chaozhang2000

  committedMar 15, 2024
  35fdf4d

Commits on Mar 14, 2024

• first add valid

  chaozhang2000

  committedMar 14, 2024
  479d331

• prepare to add valid

  chaozhang2000

  committedMar 14, 2024
  4ee3b95

• add inst cnt num reg const cnt num reg and shiftconst cnt num reg

  chaozhang2000

  committedMar 14, 2024
  eb907c1

• use add const to test PE

  chaozhang2000

  committedMar 14, 2024
  aa1b43b

Commits on Mar 13, 2024

• add Alu fureg srcmux,prepare to finish ctrlregs first then do some simulation

  chaozhang2000

  committedMar 13, 2024
  50baf71

• first add PEctrlregs

  chaozhang2000

  committedMar 13, 2024
  21aa9f2

• temp save ,first add decode and constmem to PE

  chaozhang2000

  committedMar 13, 2024
  a53366d

• almost finish PEDecode, prepare to add testbench

  chaozhang2000

  committedMar 13, 2024
  aac35b9

Commits on Mar 12, 2024

• start writing the PEdecode module

  chaozhang2000

  committedMar 12, 2024
  4d8a2ba

• change Memutil to a single Port Mem and add MemMulPort in util

  chaozhang2000

  committedMar 12, 2024
  868e08d

Commits on Mar 8, 2024

• update README

  chaozhang2000

  committedMar 8, 2024
  5c39db6

• builld use sbt

  chaozhang2000

  committedMar 8, 2024
  0c2b537

Commits on Dec 13, 2023

• nothing

  chaozhang2000

  committedDec 13, 2023
  567e22e

Commits on Aug 18, 2023

• Add Alu demo to utils and add function.scala to package func

  chaozhang2000

  committedAug 18, 2023
  248a1b0

Commits on Aug 17, 2023

• add pipelineconnect to utils which is copy from nutshell

  chaozhang2000

  committedAug 17, 2023
  c1e6d1c

Commits on Aug 16, 2023

• add Crossbar test

  chaozhang2000

  committedAug 16, 2023
  e902d5e

• add RegisterFile and Mem to utils

  chaozhang2000

  committedAug 16, 2023
  ddd2a85

Commits on Aug 15, 2023

• add Binary Mealy state machine utils

  chaozhang2000

  committedAug 15, 2023
  acfb304

• add test environment

  chaozhang2000

  committedAug 15, 2023
  08304ad

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