A DCNN accelator chip that operates on grayscale images

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📝 Table of Contents

• About
• Design
• Tools

🧐 About

A detailed low-level design of a DCNN accelerator chip that applies a CNN classifier over a grayscaled image (MNIST handwritten digits dataset). The chip is a stand-alone chip that reads the image & CNN layers from user, applies the layers (convolution / pooling) consequently, and generates the output label (0 - 9).

Design

The process is divided into 3 modules:

1. Loading the image & CNN layers (IO Module)

   • Loading the image & CNN info into the accelerator RAM will be done using compressing (SW) and passing the compressed files using a parallel port (16-bit), then your hardware will uncompress the data and save it in its designated locations.

2. Applying Layers one by one (CNN Module):

   • Applying the layers will start after the loading step is done (a done signal is passed from module 1 to module 2).
   • The CNN layers are applied consecutively (Layer1 is applied & its result is saved in the RAM, then layer2 is applied & its result is also saved in the RAM, and so on).

3. Applying fully connected layer and out the label (FC Module):

   • Finally, the last layer is a fully connected layer that is applied on the last CNN layer to generate the classification label.

IO Module

CNN Module

FC Module

⛏️ Built Using

• Verilog
• SystemVerilog
• ModelSim
• Python