diff --git a/vcs/Makefile b/vcs/Makefile index 8eb6cf2..a4aecd6 100644 --- a/vcs/Makefile +++ b/vcs/Makefile @@ -7,24 +7,20 @@ VCS_SRC_FILE = $(shell find $(RTL_DIR) -name "*.v") VCS_TB_DIR = $(abspath ./testbench) VCS_TB_FILE = $(shell find $(VCS_TB_DIR) -name "*.c") \ $(shell find $(VCS_TB_DIR) -name "*.v") +VCS_OTHER_FILE = $(shell find $(VCS_TB_DIR) -name "*.h") VCS_OPTS := -full64 +v2k -timescale=1ns/1ns \ -LDFLAGS -Wl,--no-as-needed \ - -sverilog \ + -j200 -sverilog +error+1 \ -debug_access+all \ +lint=TFIPC-L \ - +define+RANDOMIZE_GARBAGE_ASSIGN \ - +define+RANDOMIZE_INVALID_ASSIGN \ - +define+RANDOMIZE_MEM_INIT \ - +define+RANDOMIZE_DELAY=0 \ - +define+RANDOMIZE_REG_INIT \ +define+UNIT_DELAY \ +define+no_warning \ -f nanshan.f \ -f sram.f -$(EMU_VCS): $(VCS_SRC_FILE) $(VCS_TB_FILE) - export RTL_PATH=$(RTL_DIR) && export LIB_PATH=$(LIB_DIR) && export LIB_PREFIX="tt0p9v85c.v" && vcs $(VCS_OPTS) $(VCS_TB_FILE) +$(EMU_VCS): $(VCS_SRC_FILE) $(VCS_TB_FILE) $(VCS_OTHER_FILE) + export RTL_PATH=$(RTL_DIR) && export LIB_PATH=$(LIB_DIR) && export LIB_PREFIX="tt1v25c.v" && vcs $(VCS_OPTS) $(VCS_TB_FILE) clean: rm -rf simv csrc DVEfiles simv.daidir stack.info.* ucli.key diff --git a/vcs/testbench/AXI4RAM/AXI4RAM.v b/vcs/testbench/AXI4RAM_1/AXI4RAM_1.v similarity index 70% rename from vcs/testbench/AXI4RAM/AXI4RAM.v rename to vcs/testbench/AXI4RAM_1/AXI4RAM_1.v index 6e9f98a..2050455 100644 --- a/vcs/testbench/AXI4RAM/AXI4RAM.v +++ b/vcs/testbench/AXI4RAM_1/AXI4RAM_1.v @@ -1,9 +1,9 @@ -module AXI4RAM( +module AXI4RAM_1( input clock, input reset, output auto_in_aw_ready, input auto_in_aw_valid, - input [7:0] auto_in_aw_bits_id, + input [6:0] auto_in_aw_bits_id, input [39:0] auto_in_aw_bits_addr, input [7:0] auto_in_aw_bits_len, input [2:0] auto_in_aw_bits_size, @@ -19,11 +19,11 @@ module AXI4RAM( input auto_in_w_bits_last, input auto_in_b_ready, output auto_in_b_valid, - output [7:0] auto_in_b_bits_id, + output [6:0] auto_in_b_bits_id, output [1:0] auto_in_b_bits_resp, output auto_in_ar_ready, input auto_in_ar_valid, - input [7:0] auto_in_ar_bits_id, + input [6:0] auto_in_ar_bits_id, input [39:0] auto_in_ar_bits_addr, input [7:0] auto_in_ar_bits_len, input [2:0] auto_in_ar_bits_size, @@ -34,7 +34,7 @@ module AXI4RAM( input [3:0] auto_in_ar_bits_qos, input auto_in_r_ready, output auto_in_r_valid, - output [7:0] auto_in_r_bits_id, + output [6:0] auto_in_r_bits_id, output [255:0] auto_in_r_bits_data, output [1:0] auto_in_r_bits_resp, output auto_in_r_bits_last @@ -49,56 +49,56 @@ module AXI4RAM( reg [31:0] _RAND_6; reg [31:0] _RAND_7; `endif // RANDOMIZE_REG_INIT - wire RAMHelper_clk; // @[AXI4RAM.scala 54:50] - wire RAMHelper_en; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_rIdx; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_rdata; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_wIdx; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_wdata; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_wmask; // @[AXI4RAM.scala 54:50] - wire RAMHelper_wen; // @[AXI4RAM.scala 54:50] - wire RAMHelper_1_clk; // @[AXI4RAM.scala 54:50] - wire RAMHelper_1_en; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_1_rIdx; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_1_rdata; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_1_wIdx; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_1_wdata; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_1_wmask; // @[AXI4RAM.scala 54:50] - wire RAMHelper_1_wen; // @[AXI4RAM.scala 54:50] - wire RAMHelper_2_clk; // @[AXI4RAM.scala 54:50] - wire RAMHelper_2_en; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_2_rIdx; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_2_rdata; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_2_wIdx; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_2_wdata; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_2_wmask; // @[AXI4RAM.scala 54:50] - wire RAMHelper_2_wen; // @[AXI4RAM.scala 54:50] - wire RAMHelper_3_clk; // @[AXI4RAM.scala 54:50] - wire RAMHelper_3_en; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_3_rIdx; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_3_rdata; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_3_wIdx; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_3_wdata; // @[AXI4RAM.scala 54:50] - wire [63:0] RAMHelper_3_wmask; // @[AXI4RAM.scala 54:50] - wire RAMHelper_3_wen; // @[AXI4RAM.scala 54:50] - reg [1:0] state; // @[AXI4SlaveModule.scala 80:22] - wire _T_109 = state == 2'h0; // @[AXI4SlaveModule.scala 138:24] - wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 138:24] + wire RAMHelper_clk; // @[AXI4RAM.scala 56:50] + wire RAMHelper_en; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_rIdx; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_rdata; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_wIdx; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_wdata; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_wmask; // @[AXI4RAM.scala 56:50] + wire RAMHelper_wen; // @[AXI4RAM.scala 56:50] + wire RAMHelper_1_clk; // @[AXI4RAM.scala 56:50] + wire RAMHelper_1_en; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_1_rIdx; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_1_rdata; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_1_wIdx; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_1_wdata; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_1_wmask; // @[AXI4RAM.scala 56:50] + wire RAMHelper_1_wen; // @[AXI4RAM.scala 56:50] + wire RAMHelper_2_clk; // @[AXI4RAM.scala 56:50] + wire RAMHelper_2_en; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_2_rIdx; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_2_rdata; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_2_wIdx; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_2_wdata; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_2_wmask; // @[AXI4RAM.scala 56:50] + wire RAMHelper_2_wen; // @[AXI4RAM.scala 56:50] + wire RAMHelper_3_clk; // @[AXI4RAM.scala 56:50] + wire RAMHelper_3_en; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_3_rIdx; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_3_rdata; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_3_wIdx; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_3_wdata; // @[AXI4RAM.scala 56:50] + wire [63:0] RAMHelper_3_wmask; // @[AXI4RAM.scala 56:50] + wire RAMHelper_3_wen; // @[AXI4RAM.scala 56:50] + reg [1:0] state; // @[AXI4SlaveModule.scala 79:22] + wire _T_109 = state == 2'h0; // @[AXI4SlaveModule.scala 137:24] + wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 137:24] wire in_ar_valid = auto_in_ar_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T = in_ar_ready & in_ar_valid; // @[Decoupled.scala 40:37] - wire in_aw_ready = _T_109 & ~in_ar_valid; // @[AXI4SlaveModule.scala 156:35] + wire in_aw_ready = _T_109 & ~in_ar_valid; // @[AXI4SlaveModule.scala 155:35] wire in_aw_valid = auto_in_aw_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T_1 = in_aw_ready & in_aw_valid; // @[Decoupled.scala 40:37] - wire _T_117 = state == 2'h2; // @[AXI4SlaveModule.scala 157:23] - wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 157:23] + wire _T_117 = state == 2'h2; // @[AXI4SlaveModule.scala 156:23] + wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 156:23] wire in_w_valid = auto_in_w_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T_2 = in_w_ready & in_w_valid; // @[Decoupled.scala 40:37] wire in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 160:22] + wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 159:22] wire _T_3 = in_b_ready & in_b_valid; // @[Decoupled.scala 40:37] wire in_r_ready = auto_in_r_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire _T_110 = state == 2'h1; // @[AXI4SlaveModule.scala 140:23] - wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 140:23] + wire _T_110 = state == 2'h1; // @[AXI4SlaveModule.scala 139:23] + wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 139:23] wire _T_4 = in_r_ready & in_r_valid; // @[Decoupled.scala 40:37] wire [1:0] in_aw_bits_burst = auto_in_aw_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [1:0] in_ar_bits_burst = auto_in_ar_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -108,45 +108,45 @@ module AXI4RAM( wire [7:0] in_ar_bits_len = auto_in_ar_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [7:0] r; // @[Reg.scala 27:20] wire [7:0] _T_91 = _T ? in_ar_bits_len : r; // @[Hold.scala 7:48] - wire in_r_bits_last = value == _T_91; // @[AXI4SlaveModule.scala 118:32] + wire in_r_bits_last = value == _T_91; // @[AXI4SlaveModule.scala 117:32] wire _T_21 = 2'h2 == state; // @[Conditional.scala 37:30] wire in_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 97:42 AXI4SlaveModule.scala 98:15 AXI4SlaveModule.scala 80:22] + wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 96:42 AXI4SlaveModule.scala 97:15 AXI4SlaveModule.scala 79:22] wire _T_24 = 2'h3 == state; // @[Conditional.scala 37:30] - wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 102:24 AXI4SlaveModule.scala 103:15 AXI4SlaveModule.scala 80:22] - wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 80:22] + wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 101:24 AXI4SlaveModule.scala 102:15 AXI4SlaveModule.scala 79:22] + wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 79:22] wire [31:0] in_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [39:0] r_1; // @[Reg.scala 27:20] wire [39:0] in_ar_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [39:0] _GEN_10 = _T ? in_ar_bits_addr : r_1; // @[Reg.scala 28:19 Reg.scala 28:23 Reg.scala 27:20] wire [7:0] _value_T_1 = value + 8'h1; // @[Counter.scala 76:24] - wire _T_98 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 129:26] - wire _T_99 = in_ar_bits_len == 8'h0 | _T_98; // @[AXI4SlaveModule.scala 128:32] - wire _T_100 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 130:26] - wire _T_101 = _T_99 | _T_100; // @[AXI4SlaveModule.scala 129:34] - wire _T_102 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 131:26] - wire _T_103 = _T_101 | _T_102; // @[AXI4SlaveModule.scala 130:34] - wire _T_104 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 132:26] - wire _T_105 = _T_103 | _T_104; // @[AXI4SlaveModule.scala 131:34] + wire _T_98 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 128:26] + wire _T_99 = in_ar_bits_len == 8'h0 | _T_98; // @[AXI4SlaveModule.scala 127:32] + wire _T_100 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 129:26] + wire _T_101 = _T_99 | _T_100; // @[AXI4SlaveModule.scala 128:34] + wire _T_102 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 130:26] + wire _T_103 = _T_101 | _T_102; // @[AXI4SlaveModule.scala 129:34] + wire _T_104 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 131:26] + wire _T_105 = _T_103 | _T_104; // @[AXI4SlaveModule.scala 130:34] reg [7:0] value_1; // @[Counter.scala 60:40] reg [39:0] r_2; // @[Reg.scala 27:20] wire [39:0] in_aw_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [39:0] _GEN_13 = _T_1 ? in_aw_bits_addr : r_2; // @[Reg.scala 28:19 Reg.scala 28:23 Reg.scala 27:20] wire [7:0] _value_T_3 = value_1 + 8'h1; // @[Counter.scala 76:24] - reg [7:0] r_3; // @[Reg.scala 15:16] - wire [7:0] in_aw_bits_id = auto_in_aw_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - reg [7:0] r_5; // @[Reg.scala 15:16] - wire [7:0] in_ar_bits_id = auto_in_ar_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [39:0] _T_124 = _GEN_13 - 40'h80000000; // @[AXI4RAM.scala 44:36] - wire [30:0] _GEN_18 = {{23'd0}, value_1}; // @[AXI4RAM.scala 48:29] - wire [30:0] wIdx = _T_124[35:5] + _GEN_18; // @[AXI4RAM.scala 48:29] - wire [39:0] _T_129 = _GEN_10 - 40'h80000000; // @[AXI4RAM.scala 44:36] - wire [30:0] _GEN_19 = {{23'd0}, value}; // @[AXI4RAM.scala 49:29] - wire [30:0] rIdx = _T_129[35:5] + _GEN_19; // @[AXI4RAM.scala 49:29] - wire [32:0] _T_141 = {rIdx, 2'h0}; // @[AXI4RAM.scala 58:31] - wire [33:0] _T_142 = {{1'd0}, _T_141}; // @[AXI4RAM.scala 58:49] - wire [32:0] _T_144 = {wIdx, 2'h0}; // @[AXI4RAM.scala 59:31] - wire [33:0] _T_145 = {{1'd0}, _T_144}; // @[AXI4RAM.scala 59:49] + reg [6:0] r_3; // @[Reg.scala 15:16] + wire [6:0] in_aw_bits_id = auto_in_aw_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + reg [6:0] r_5; // @[Reg.scala 15:16] + wire [6:0] in_ar_bits_id = auto_in_ar_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [39:0] _T_124 = _GEN_13 - 40'h80000000; // @[AXI4RAM.scala 46:36] + wire [27:0] _GEN_18 = {{20'd0}, value_1}; // @[AXI4RAM.scala 50:29] + wire [27:0] wIdx = _T_124[32:5] + _GEN_18; // @[AXI4RAM.scala 50:29] + wire [39:0] _T_129 = _GEN_10 - 40'h80000000; // @[AXI4RAM.scala 46:36] + wire [27:0] _GEN_19 = {{20'd0}, value}; // @[AXI4RAM.scala 51:29] + wire [27:0] rIdx = _T_129[32:5] + _GEN_19; // @[AXI4RAM.scala 51:29] + wire [29:0] _T_141 = {rIdx, 2'h0}; // @[AXI4RAM.scala 60:31] + wire [30:0] _T_142 = {{1'd0}, _T_141}; // @[AXI4RAM.scala 60:49] + wire [29:0] _T_144 = {wIdx, 2'h0}; // @[AXI4RAM.scala 61:31] + wire [30:0] _T_145 = {{1'd0}, _T_144}; // @[AXI4RAM.scala 61:49] wire [255:0] in_w_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [7:0] lo_lo_lo_1 = in_w_bits_strb[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] lo_lo_hi_1 = in_w_bits_strb[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] @@ -158,8 +158,8 @@ module AXI4RAM( wire [7:0] hi_hi_hi_1 = in_w_bits_strb[7] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [31:0] lo_1 = {lo_hi_hi_1,lo_hi_lo_1,lo_lo_hi_1,lo_lo_lo_1}; // @[Cat.scala 30:58] wire [31:0] hi_1 = {hi_hi_hi_1,hi_hi_lo_1,hi_lo_hi_1,hi_lo_lo_1}; // @[Cat.scala 30:58] - wire [32:0] _T_174 = _T_141 + 33'h1; // @[AXI4RAM.scala 58:49] - wire [32:0] _T_177 = _T_144 + 33'h1; // @[AXI4RAM.scala 59:49] + wire [29:0] _T_174 = _T_141 + 30'h1; // @[AXI4RAM.scala 60:49] + wire [29:0] _T_177 = _T_144 + 30'h1; // @[AXI4RAM.scala 61:49] wire [7:0] lo_lo_lo_2 = in_w_bits_strb[8] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] lo_lo_hi_2 = in_w_bits_strb[9] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] lo_hi_lo_2 = in_w_bits_strb[10] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] @@ -170,8 +170,8 @@ module AXI4RAM( wire [7:0] hi_hi_hi_2 = in_w_bits_strb[15] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [31:0] lo_2 = {lo_hi_hi_2,lo_hi_lo_2,lo_lo_hi_2,lo_lo_lo_2}; // @[Cat.scala 30:58] wire [31:0] hi_2 = {hi_hi_hi_2,hi_hi_lo_2,hi_lo_hi_2,hi_lo_lo_2}; // @[Cat.scala 30:58] - wire [32:0] _T_205 = _T_141 + 33'h2; // @[AXI4RAM.scala 58:49] - wire [32:0] _T_208 = _T_144 + 33'h2; // @[AXI4RAM.scala 59:49] + wire [29:0] _T_205 = _T_141 + 30'h2; // @[AXI4RAM.scala 60:49] + wire [29:0] _T_208 = _T_144 + 30'h2; // @[AXI4RAM.scala 61:49] wire [7:0] lo_lo_lo_3 = in_w_bits_strb[16] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] lo_lo_hi_3 = in_w_bits_strb[17] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] lo_hi_lo_3 = in_w_bits_strb[18] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] @@ -182,8 +182,8 @@ module AXI4RAM( wire [7:0] hi_hi_hi_3 = in_w_bits_strb[23] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [31:0] lo_3 = {lo_hi_hi_3,lo_hi_lo_3,lo_lo_hi_3,lo_lo_lo_3}; // @[Cat.scala 30:58] wire [31:0] hi_3 = {hi_hi_hi_3,hi_hi_lo_3,hi_lo_hi_3,hi_lo_lo_3}; // @[Cat.scala 30:58] - wire [32:0] _T_236 = _T_141 + 33'h3; // @[AXI4RAM.scala 58:49] - wire [32:0] _T_239 = _T_144 + 33'h3; // @[AXI4RAM.scala 59:49] + wire [29:0] _T_236 = _T_141 + 30'h3; // @[AXI4RAM.scala 60:49] + wire [29:0] _T_239 = _T_144 + 30'h3; // @[AXI4RAM.scala 61:49] wire [7:0] lo_lo_lo_4 = in_w_bits_strb[24] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] lo_lo_hi_4 = in_w_bits_strb[25] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] lo_hi_lo_4 = in_w_bits_strb[26] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] @@ -201,17 +201,17 @@ module AXI4RAM( wire [3:0] in_aw_bits_cache = auto_in_aw_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [2:0] in_aw_bits_prot = auto_in_aw_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_aw_bits_qos = auto_in_aw_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [7:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 162:16] - wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 159:18] + wire [6:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 161:16] + wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 158:18] wire [2:0] in_ar_bits_size = auto_in_ar_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire in_ar_bits_lock = auto_in_ar_bits_lock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_ar_bits_cache = auto_in_ar_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [2:0] in_ar_bits_prot = auto_in_ar_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_ar_bits_qos = auto_in_ar_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [7:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 164:16] + wire [6:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 163:16] wire [255:0] in_r_bits_data = rdata; // @[Cat.scala 30:58] - wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 139:18] - RAMHelper RAMHelper ( // @[AXI4RAM.scala 54:50] + wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 138:18] + RAMHelper RAMHelper ( // @[AXI4RAM.scala 56:50] .clk(RAMHelper_clk), .en(RAMHelper_en), .rIdx(RAMHelper_rIdx), @@ -221,7 +221,7 @@ module AXI4RAM( .wmask(RAMHelper_wmask), .wen(RAMHelper_wen) ); - RAMHelper RAMHelper_1 ( // @[AXI4RAM.scala 54:50] + RAMHelper RAMHelper_1 ( // @[AXI4RAM.scala 56:50] .clk(RAMHelper_1_clk), .en(RAMHelper_1_en), .rIdx(RAMHelper_1_rIdx), @@ -231,7 +231,7 @@ module AXI4RAM( .wmask(RAMHelper_1_wmask), .wen(RAMHelper_1_wen) ); - RAMHelper RAMHelper_2 ( // @[AXI4RAM.scala 54:50] + RAMHelper RAMHelper_2 ( // @[AXI4RAM.scala 56:50] .clk(RAMHelper_2_clk), .en(RAMHelper_2_en), .rIdx(RAMHelper_2_rIdx), @@ -241,7 +241,7 @@ module AXI4RAM( .wmask(RAMHelper_2_wmask), .wen(RAMHelper_2_wen) ); - RAMHelper RAMHelper_3 ( // @[AXI4RAM.scala 54:50] + RAMHelper RAMHelper_3 ( // @[AXI4RAM.scala 56:50] .clk(RAMHelper_3_clk), .en(RAMHelper_3_en), .rIdx(RAMHelper_3_rIdx), @@ -262,46 +262,46 @@ module AXI4RAM( assign auto_in_r_bits_data = in_r_bits_data; // @[LazyModule.scala 309:16] assign auto_in_r_bits_resp = in_b_bits_resp; // @[LazyModule.scala 309:16] assign auto_in_r_bits_last = in_r_bits_last; // @[LazyModule.scala 309:16] - assign RAMHelper_clk = clock; // @[AXI4RAM.scala 56:22] - assign RAMHelper_en = ~reset & (_T_110 | _T_117); // @[AXI4RAM.scala 57:41] - assign RAMHelper_rIdx = {{31'd0}, _T_142[32:0]}; // @[AXI4RAM.scala 58:49] - assign RAMHelper_wIdx = {{31'd0}, _T_145[32:0]}; // @[AXI4RAM.scala 59:49] - assign RAMHelper_wdata = in_w_bits_data[63:0]; // @[AXI4RAM.scala 60:39] + assign RAMHelper_clk = clock; // @[AXI4RAM.scala 58:22] + assign RAMHelper_en = ~reset & (_T_110 | _T_117); // @[AXI4RAM.scala 59:41] + assign RAMHelper_rIdx = {{34'd0}, _T_142[29:0]}; // @[AXI4RAM.scala 60:49] + assign RAMHelper_wIdx = {{34'd0}, _T_145[29:0]}; // @[AXI4RAM.scala 61:49] + assign RAMHelper_wdata = in_w_bits_data[63:0]; // @[AXI4RAM.scala 62:39] assign RAMHelper_wmask = {hi_1,lo_1}; // @[Cat.scala 30:58] assign RAMHelper_wen = in_w_ready & in_w_valid; // @[Decoupled.scala 40:37] - assign RAMHelper_1_clk = clock; // @[AXI4RAM.scala 56:22] - assign RAMHelper_1_en = ~reset & (_T_110 | _T_117); // @[AXI4RAM.scala 57:41] - assign RAMHelper_1_rIdx = {{31'd0}, _T_174}; // @[AXI4RAM.scala 58:49] - assign RAMHelper_1_wIdx = {{31'd0}, _T_177}; // @[AXI4RAM.scala 59:49] - assign RAMHelper_1_wdata = in_w_bits_data[127:64]; // @[AXI4RAM.scala 60:39] + assign RAMHelper_1_clk = clock; // @[AXI4RAM.scala 58:22] + assign RAMHelper_1_en = ~reset & (_T_110 | _T_117); // @[AXI4RAM.scala 59:41] + assign RAMHelper_1_rIdx = {{34'd0}, _T_174}; // @[AXI4RAM.scala 60:49] + assign RAMHelper_1_wIdx = {{34'd0}, _T_177}; // @[AXI4RAM.scala 61:49] + assign RAMHelper_1_wdata = in_w_bits_data[127:64]; // @[AXI4RAM.scala 62:39] assign RAMHelper_1_wmask = {hi_2,lo_2}; // @[Cat.scala 30:58] assign RAMHelper_1_wen = in_w_ready & in_w_valid; // @[Decoupled.scala 40:37] - assign RAMHelper_2_clk = clock; // @[AXI4RAM.scala 56:22] - assign RAMHelper_2_en = ~reset & (_T_110 | _T_117); // @[AXI4RAM.scala 57:41] - assign RAMHelper_2_rIdx = {{31'd0}, _T_205}; // @[AXI4RAM.scala 58:49] - assign RAMHelper_2_wIdx = {{31'd0}, _T_208}; // @[AXI4RAM.scala 59:49] - assign RAMHelper_2_wdata = in_w_bits_data[191:128]; // @[AXI4RAM.scala 60:39] + assign RAMHelper_2_clk = clock; // @[AXI4RAM.scala 58:22] + assign RAMHelper_2_en = ~reset & (_T_110 | _T_117); // @[AXI4RAM.scala 59:41] + assign RAMHelper_2_rIdx = {{34'd0}, _T_205}; // @[AXI4RAM.scala 60:49] + assign RAMHelper_2_wIdx = {{34'd0}, _T_208}; // @[AXI4RAM.scala 61:49] + assign RAMHelper_2_wdata = in_w_bits_data[191:128]; // @[AXI4RAM.scala 62:39] assign RAMHelper_2_wmask = {hi_3,lo_3}; // @[Cat.scala 30:58] assign RAMHelper_2_wen = in_w_ready & in_w_valid; // @[Decoupled.scala 40:37] - assign RAMHelper_3_clk = clock; // @[AXI4RAM.scala 56:22] - assign RAMHelper_3_en = ~reset & (_T_110 | _T_117); // @[AXI4RAM.scala 57:41] - assign RAMHelper_3_rIdx = {{31'd0}, _T_236}; // @[AXI4RAM.scala 58:49] - assign RAMHelper_3_wIdx = {{31'd0}, _T_239}; // @[AXI4RAM.scala 59:49] - assign RAMHelper_3_wdata = in_w_bits_data[255:192]; // @[AXI4RAM.scala 60:39] + assign RAMHelper_3_clk = clock; // @[AXI4RAM.scala 58:22] + assign RAMHelper_3_en = ~reset & (_T_110 | _T_117); // @[AXI4RAM.scala 59:41] + assign RAMHelper_3_rIdx = {{34'd0}, _T_236}; // @[AXI4RAM.scala 60:49] + assign RAMHelper_3_wIdx = {{34'd0}, _T_239}; // @[AXI4RAM.scala 61:49] + assign RAMHelper_3_wdata = in_w_bits_data[255:192]; // @[AXI4RAM.scala 62:39] assign RAMHelper_3_wmask = {hi_4,lo_4}; // @[Cat.scala 30:58] assign RAMHelper_3_wen = in_w_ready & in_w_valid; // @[Decoupled.scala 40:37] always @(posedge clock) begin - if (reset) begin // @[AXI4SlaveModule.scala 80:22] - state <= 2'h0; // @[AXI4SlaveModule.scala 80:22] + if (reset) begin // @[AXI4SlaveModule.scala 79:22] + state <= 2'h0; // @[AXI4SlaveModule.scala 79:22] end else if (_T_15) begin // @[Conditional.scala 40:58] - if (_T_1) begin // @[AXI4SlaveModule.scala 87:25] - state <= 2'h2; // @[AXI4SlaveModule.scala 88:15] - end else if (_T) begin // @[AXI4SlaveModule.scala 84:25] - state <= 2'h1; // @[AXI4SlaveModule.scala 85:15] + if (_T_1) begin // @[AXI4SlaveModule.scala 86:25] + state <= 2'h2; // @[AXI4SlaveModule.scala 87:15] + end else if (_T) begin // @[AXI4SlaveModule.scala 83:25] + state <= 2'h1; // @[AXI4SlaveModule.scala 84:15] end end else if (_T_18) begin // @[Conditional.scala 39:67] - if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 92:42] - state <= 2'h0; // @[AXI4SlaveModule.scala 93:15] + if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 91:42] + state <= 2'h0; // @[AXI4SlaveModule.scala 92:15] end end else if (_T_21) begin // @[Conditional.scala 39:67] state <= _GEN_3; @@ -310,9 +310,9 @@ module AXI4RAM( end if (reset) begin // @[Counter.scala 60:40] value <= 8'h0; // @[Counter.scala 60:40] - end else if (_T_4) begin // @[AXI4SlaveModule.scala 120:23] - if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 122:28] - value <= 8'h0; // @[AXI4SlaveModule.scala 123:17] + end else if (_T_4) begin // @[AXI4SlaveModule.scala 119:23] + if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 121:28] + value <= 8'h0; // @[AXI4SlaveModule.scala 122:17] end else begin value <= _value_T_1; // @[Counter.scala 76:15] end @@ -329,9 +329,9 @@ module AXI4RAM( end if (reset) begin // @[Counter.scala 60:40] value_1 <= 8'h0; // @[Counter.scala 60:40] - end else if (_T_2) begin // @[AXI4SlaveModule.scala 147:23] - if (in_w_bits_last) begin // @[AXI4SlaveModule.scala 149:28] - value_1 <= 8'h0; // @[AXI4SlaveModule.scala 150:17] + end else if (_T_2) begin // @[AXI4SlaveModule.scala 146:23] + if (in_w_bits_last) begin // @[AXI4SlaveModule.scala 148:28] + value_1 <= 8'h0; // @[AXI4SlaveModule.scala 149:17] end else begin value_1 <= _value_T_3; // @[Counter.scala 76:15] end @@ -353,70 +353,37 @@ module AXI4RAM( `endif if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin $fwrite(32'h80000002, - "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:72 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" - ); // @[AXI4SlaveModule.scala 72:11] + "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:71 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" + ); // @[AXI4SlaveModule.scala 71:11] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 72:11] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin $fwrite(32'h80000002, - "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:75 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" - ); // @[AXI4SlaveModule.scala 75:11] + "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:74 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" + ); // @[AXI4SlaveModule.scala 74:11] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 75:11] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T & ~(_T_105 | reset)) begin - $fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:127 assert(\n"); // @[AXI4SlaveModule.scala 127:13] + $fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:126 assert(\n"); // @[AXI4SlaveModule.scala 126:13] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS - `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T & ~(_T_105 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 127:13] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS end // Register and memory initialization `ifdef RANDOMIZE_GARBAGE_ASSIGN @@ -467,9 +434,9 @@ initial begin _RAND_5 = {2{`RANDOM}}; r_2 = _RAND_5[39:0]; _RAND_6 = {1{`RANDOM}}; - r_3 = _RAND_6[7:0]; + r_3 = _RAND_6[6:0]; _RAND_7 = {1{`RANDOM}}; - r_5 = _RAND_7[7:0]; + r_5 = _RAND_7[6:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end // initial @@ -478,3 +445,4 @@ end // initial `endif `endif // SYNTHESIS endmodule + diff --git a/vcs/testbench/AXI4RAM/RAMHelper.v b/vcs/testbench/AXI4RAM_1/RAMHelper.v similarity index 99% rename from vcs/testbench/AXI4RAM/RAMHelper.v rename to vcs/testbench/AXI4RAM_1/RAMHelper.v index 4472116..cd908dd 100644 --- a/vcs/testbench/AXI4RAM/RAMHelper.v +++ b/vcs/testbench/AXI4RAM_1/RAMHelper.v @@ -28,3 +28,4 @@ module RAMHelper( end endmodule + diff --git a/vcs/testbench/SimMMIO/AXI4DummySD.v b/vcs/testbench/SimMMIO/AXI4DummySD.v index 1b5eaab..74bfd33 100644 --- a/vcs/testbench/SimMMIO/AXI4DummySD.v +++ b/vcs/testbench/SimMMIO/AXI4DummySD.v @@ -62,22 +62,22 @@ module AXI4DummySD( wire [31:0] sdHelper_data; // @[AXI4DummySD.scala 108:26] wire sdHelper_setAddr; // @[AXI4DummySD.scala 108:26] wire [31:0] sdHelper_addr; // @[AXI4DummySD.scala 108:26] - reg [1:0] state; // @[AXI4SlaveModule.scala 80:22] - wire _T_61 = state == 2'h0; // @[AXI4SlaveModule.scala 138:24] - wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 138:24] + reg [1:0] state; // @[AXI4SlaveModule.scala 79:22] + wire _T_61 = state == 2'h0; // @[AXI4SlaveModule.scala 137:24] + wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 137:24] wire in_ar_valid = auto_in_ar_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T = in_ar_ready & in_ar_valid; // @[Decoupled.scala 40:37] - wire in_aw_ready = _T_61 & ~in_ar_valid; // @[AXI4SlaveModule.scala 156:35] + wire in_aw_ready = _T_61 & ~in_ar_valid; // @[AXI4SlaveModule.scala 155:35] wire in_aw_valid = auto_in_aw_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T_1 = in_aw_ready & in_aw_valid; // @[Decoupled.scala 40:37] - wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 157:23] + wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 156:23] wire in_w_valid = auto_in_w_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T_2 = in_w_ready & in_w_valid; // @[Decoupled.scala 40:37] wire in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 160:22] + wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 159:22] wire _T_3 = in_b_ready & in_b_valid; // @[Decoupled.scala 40:37] wire in_r_ready = auto_in_r_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 140:23] + wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 139:23] wire _T_4 = in_r_ready & in_r_valid; // @[Decoupled.scala 40:37] wire [1:0] in_aw_bits_burst = auto_in_aw_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [1:0] in_ar_bits_burst = auto_in_ar_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -87,26 +87,26 @@ module AXI4DummySD( wire [7:0] in_ar_bits_len = auto_in_ar_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [7:0] r; // @[Reg.scala 27:20] wire [7:0] _T_43 = _T ? in_ar_bits_len : r; // @[Hold.scala 7:48] - wire in_r_bits_last = value == _T_43; // @[AXI4SlaveModule.scala 118:32] + wire in_r_bits_last = value == _T_43; // @[AXI4SlaveModule.scala 117:32] wire _T_21 = 2'h2 == state; // @[Conditional.scala 37:30] wire in_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 97:42 AXI4SlaveModule.scala 98:15 AXI4SlaveModule.scala 80:22] + wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 96:42 AXI4SlaveModule.scala 97:15 AXI4SlaveModule.scala 79:22] wire _T_24 = 2'h3 == state; // @[Conditional.scala 37:30] - wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 102:24 AXI4SlaveModule.scala 103:15 AXI4SlaveModule.scala 80:22] - wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 80:22] + wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 101:24 AXI4SlaveModule.scala 102:15 AXI4SlaveModule.scala 79:22] + wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 79:22] wire [7:0] in_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [30:0] r_1; // @[Reg.scala 27:20] wire [30:0] in_ar_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [30:0] _GEN_10 = _T ? in_ar_bits_addr : r_1; // @[Reg.scala 28:19 Reg.scala 28:23 Reg.scala 27:20] wire [7:0] _value_T_1 = value + 8'h1; // @[Counter.scala 76:24] - wire _T_50 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 129:26] - wire _T_51 = in_ar_bits_len == 8'h0 | _T_50; // @[AXI4SlaveModule.scala 128:32] - wire _T_52 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 130:26] - wire _T_53 = _T_51 | _T_52; // @[AXI4SlaveModule.scala 129:34] - wire _T_54 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 131:26] - wire _T_55 = _T_53 | _T_54; // @[AXI4SlaveModule.scala 130:34] - wire _T_56 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 132:26] - wire _T_57 = _T_55 | _T_56; // @[AXI4SlaveModule.scala 131:34] + wire _T_50 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 128:26] + wire _T_51 = in_ar_bits_len == 8'h0 | _T_50; // @[AXI4SlaveModule.scala 127:32] + wire _T_52 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 129:26] + wire _T_53 = _T_51 | _T_52; // @[AXI4SlaveModule.scala 128:34] + wire _T_54 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 130:26] + wire _T_55 = _T_53 | _T_54; // @[AXI4SlaveModule.scala 129:34] + wire _T_56 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 131:26] + wire _T_57 = _T_55 | _T_56; // @[AXI4SlaveModule.scala 130:34] reg [30:0] r_2; // @[Reg.scala 27:20] wire [30:0] in_aw_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [30:0] _GEN_13 = _T_1 ? in_aw_bits_addr : r_2; // @[Reg.scala 28:19 Reg.scala 28:23 Reg.scala 27:20] @@ -211,16 +211,16 @@ module AXI4DummySD( wire [3:0] in_aw_bits_cache = auto_in_aw_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [2:0] in_aw_bits_prot = auto_in_aw_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_aw_bits_qos = auto_in_aw_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 162:16] - wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 159:18] + wire [1:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 161:16] + wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 158:18] wire [2:0] in_ar_bits_size = auto_in_ar_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire in_ar_bits_lock = auto_in_ar_bits_lock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_ar_bits_cache = auto_in_ar_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [2:0] in_ar_bits_prot = auto_in_ar_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_ar_bits_qos = auto_in_ar_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 164:16] + wire [1:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 163:16] wire [63:0] in_r_bits_data = {hi_2,hi_2}; // @[Cat.scala 30:58] - wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 139:18] + wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 138:18] SDHelper sdHelper ( // @[AXI4DummySD.scala 108:26] .clk(sdHelper_clk), .ren(sdHelper_ren), @@ -244,17 +244,17 @@ module AXI4DummySD( assign sdHelper_setAddr = _T_2 & _GEN_13[12:0] == 13'h0 & _GEN_38; // @[RegMap.scala 14:48] assign sdHelper_addr = regs_1; // @[AXI4DummySD.scala 112:22] always @(posedge clock) begin - if (reset) begin // @[AXI4SlaveModule.scala 80:22] - state <= 2'h0; // @[AXI4SlaveModule.scala 80:22] + if (reset) begin // @[AXI4SlaveModule.scala 79:22] + state <= 2'h0; // @[AXI4SlaveModule.scala 79:22] end else if (_T_15) begin // @[Conditional.scala 40:58] - if (_T_1) begin // @[AXI4SlaveModule.scala 87:25] - state <= 2'h2; // @[AXI4SlaveModule.scala 88:15] - end else if (_T) begin // @[AXI4SlaveModule.scala 84:25] - state <= 2'h1; // @[AXI4SlaveModule.scala 85:15] + if (_T_1) begin // @[AXI4SlaveModule.scala 86:25] + state <= 2'h2; // @[AXI4SlaveModule.scala 87:15] + end else if (_T) begin // @[AXI4SlaveModule.scala 83:25] + state <= 2'h1; // @[AXI4SlaveModule.scala 84:15] end end else if (_T_18) begin // @[Conditional.scala 39:67] - if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 92:42] - state <= 2'h0; // @[AXI4SlaveModule.scala 93:15] + if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 91:42] + state <= 2'h0; // @[AXI4SlaveModule.scala 92:15] end end else if (_T_21) begin // @[Conditional.scala 39:67] state <= _GEN_3; @@ -263,9 +263,9 @@ module AXI4DummySD( end if (reset) begin // @[Counter.scala 60:40] value <= 8'h0; // @[Counter.scala 60:40] - end else if (_T_4) begin // @[AXI4SlaveModule.scala 120:23] - if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 122:28] - value <= 8'h0; // @[AXI4SlaveModule.scala 123:17] + end else if (_T_4) begin // @[AXI4SlaveModule.scala 119:23] + if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 121:28] + value <= 8'h0; // @[AXI4SlaveModule.scala 122:17] end else begin value <= _value_T_1; // @[Counter.scala 76:15] end @@ -366,70 +366,37 @@ module AXI4DummySD( `endif if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin $fwrite(32'h80000002, - "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:72 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" - ); // @[AXI4SlaveModule.scala 72:11] + "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:71 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" + ); // @[AXI4SlaveModule.scala 71:11] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 72:11] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin $fwrite(32'h80000002, - "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:75 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" - ); // @[AXI4SlaveModule.scala 75:11] + "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:74 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" + ); // @[AXI4SlaveModule.scala 74:11] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 75:11] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T & ~(_T_57 | reset)) begin - $fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:127 assert(\n"); // @[AXI4SlaveModule.scala 127:13] + $fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:126 assert(\n"); // @[AXI4SlaveModule.scala 126:13] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS - `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T & ~(_T_57 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 127:13] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS end // Register and memory initialization `ifdef RANDOMIZE_GARBAGE_ASSIGN @@ -507,3 +474,4 @@ end // initial `endif `endif // SYNTHESIS endmodule + diff --git a/vcs/testbench/SimMMIO/AXI4Flash.v b/vcs/testbench/SimMMIO/AXI4Flash.v index b90a663..5a0ab6b 100644 --- a/vcs/testbench/SimMMIO/AXI4Flash.v +++ b/vcs/testbench/SimMMIO/AXI4Flash.v @@ -47,22 +47,26 @@ module AXI4Flash( reg [31:0] _RAND_4; reg [31:0] _RAND_5; `endif // RANDOMIZE_REG_INIT - reg [1:0] state; // @[AXI4SlaveModule.scala 80:22] - wire _T_61 = state == 2'h0; // @[AXI4SlaveModule.scala 138:24] - wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 138:24] + wire flash_clk; // @[AXI4Flash.scala 51:23] + wire flash_ren; // @[AXI4Flash.scala 51:23] + wire [63:0] flash_data; // @[AXI4Flash.scala 51:23] + wire [31:0] flash_addr; // @[AXI4Flash.scala 51:23] + reg [1:0] state; // @[AXI4SlaveModule.scala 79:22] + wire _T_61 = state == 2'h0; // @[AXI4SlaveModule.scala 137:24] + wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 137:24] wire in_ar_valid = auto_in_ar_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T = in_ar_ready & in_ar_valid; // @[Decoupled.scala 40:37] - wire in_aw_ready = _T_61 & ~in_ar_valid; // @[AXI4SlaveModule.scala 156:35] + wire in_aw_ready = _T_61 & ~in_ar_valid; // @[AXI4SlaveModule.scala 155:35] wire in_aw_valid = auto_in_aw_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T_1 = in_aw_ready & in_aw_valid; // @[Decoupled.scala 40:37] - wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 157:23] + wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 156:23] wire in_w_valid = auto_in_w_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T_2 = in_w_ready & in_w_valid; // @[Decoupled.scala 40:37] wire in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 160:22] + wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 159:22] wire _T_3 = in_b_ready & in_b_valid; // @[Decoupled.scala 40:37] wire in_r_ready = auto_in_r_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 140:23] + wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 139:23] wire _T_4 = in_r_ready & in_r_valid; // @[Decoupled.scala 40:37] wire [1:0] in_aw_bits_burst = auto_in_aw_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [1:0] in_ar_bits_burst = auto_in_ar_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -72,55 +76,32 @@ module AXI4Flash( wire [7:0] in_ar_bits_len = auto_in_ar_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [7:0] r; // @[Reg.scala 27:20] wire [7:0] _T_43 = _T ? in_ar_bits_len : r; // @[Hold.scala 7:48] - wire in_r_bits_last = value == _T_43; // @[AXI4SlaveModule.scala 118:32] + wire in_r_bits_last = value == _T_43; // @[AXI4SlaveModule.scala 117:32] wire _T_21 = 2'h2 == state; // @[Conditional.scala 37:30] wire in_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 97:42 AXI4SlaveModule.scala 98:15 AXI4SlaveModule.scala 80:22] + wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 96:42 AXI4SlaveModule.scala 97:15 AXI4SlaveModule.scala 79:22] wire _T_24 = 2'h3 == state; // @[Conditional.scala 37:30] - wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 102:24 AXI4SlaveModule.scala 103:15 AXI4SlaveModule.scala 80:22] - wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 80:22] + wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 101:24 AXI4SlaveModule.scala 102:15 AXI4SlaveModule.scala 79:22] + wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 79:22] wire [7:0] in_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [28:0] r_1; // @[Reg.scala 27:20] wire [28:0] in_ar_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [28:0] _GEN_10 = _T ? in_ar_bits_addr : r_1; // @[Reg.scala 28:19 Reg.scala 28:23 Reg.scala 27:20] wire [7:0] _value_T_1 = value + 8'h1; // @[Counter.scala 76:24] - wire _T_50 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 129:26] - wire _T_51 = in_ar_bits_len == 8'h0 | _T_50; // @[AXI4SlaveModule.scala 128:32] - wire _T_52 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 130:26] - wire _T_53 = _T_51 | _T_52; // @[AXI4SlaveModule.scala 129:34] - wire _T_54 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 131:26] - wire _T_55 = _T_53 | _T_54; // @[AXI4SlaveModule.scala 130:34] - wire _T_56 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 132:26] - wire _T_57 = _T_55 | _T_56; // @[AXI4SlaveModule.scala 131:34] + wire _T_50 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 128:26] + wire _T_51 = in_ar_bits_len == 8'h0 | _T_50; // @[AXI4SlaveModule.scala 127:32] + wire _T_52 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 129:26] + wire _T_53 = _T_51 | _T_52; // @[AXI4SlaveModule.scala 128:34] + wire _T_54 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 130:26] + wire _T_55 = _T_53 | _T_54; // @[AXI4SlaveModule.scala 129:34] + wire _T_56 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 131:26] + wire _T_57 = _T_55 | _T_56; // @[AXI4SlaveModule.scala 130:34] wire [28:0] in_aw_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [1:0] r_3; // @[Reg.scala 15:16] wire [1:0] in_aw_bits_id = auto_in_aw_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [1:0] r_5; // @[Reg.scala 15:16] wire [1:0] in_ar_bits_id = auto_in_ar_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [29:0] _T_75 = {{1'd0}, _GEN_10}; // @[AXI4Flash.scala 30:48] - wire _T_97 = 13'h0 == _T_75[12:0]; // @[LookupTree.scala 8:34] - wire _T_98 = 13'h4 == _T_75[12:0]; // @[LookupTree.scala 8:34] - wire _T_99 = 13'h8 == _T_75[12:0]; // @[LookupTree.scala 8:34] - wire [20:0] _T_100 = _T_97 ? 21'h10029b : 21'h0; // @[Mux.scala 27:72] - wire [24:0] _T_101 = _T_98 ? 25'h1f29293 : 25'h0; // @[Mux.scala 27:72] - wire [17:0] _T_102 = _T_99 ? 18'h28067 : 18'h0; // @[Mux.scala 27:72] - wire [24:0] _GEN_18 = {{4'd0}, _T_100}; // @[Mux.scala 27:72] - wire [24:0] _T_103 = _GEN_18 | _T_101; // @[Mux.scala 27:72] - wire [24:0] _GEN_19 = {{7'd0}, _T_102}; // @[Mux.scala 27:72] - wire [24:0] _T_104 = _T_103 | _GEN_19; // @[Mux.scala 27:72] - wire [28:0] _T_106 = _GEN_10 + 29'h4; // @[AXI4Flash.scala 30:48] - wire _T_127 = 13'h0 == _T_106[12:0]; // @[LookupTree.scala 8:34] - wire _T_128 = 13'h4 == _T_106[12:0]; // @[LookupTree.scala 8:34] - wire _T_129 = 13'h8 == _T_106[12:0]; // @[LookupTree.scala 8:34] - wire [20:0] _T_130 = _T_127 ? 21'h10029b : 21'h0; // @[Mux.scala 27:72] - wire [24:0] _T_131 = _T_128 ? 25'h1f29293 : 25'h0; // @[Mux.scala 27:72] - wire [17:0] _T_132 = _T_129 ? 18'h28067 : 18'h0; // @[Mux.scala 27:72] - wire [24:0] _GEN_20 = {{4'd0}, _T_130}; // @[Mux.scala 27:72] - wire [24:0] _T_133 = _GEN_20 | _T_131; // @[Mux.scala 27:72] - wire [24:0] _GEN_21 = {{7'd0}, _T_132}; // @[Mux.scala 27:72] - wire [24:0] _T_134 = _T_133 | _GEN_21; // @[Mux.scala 27:72] - wire [31:0] rdata_1 = {{7'd0}, _T_134}; // @[AXI4Flash.scala 28:21 RegMap.scala 12:11] - wire [31:0] rdata_0 = {{7'd0}, _T_104}; // @[AXI4Flash.scala 28:21 RegMap.scala 12:11] + wire [15:0] lo_1 = _GEN_10[15:0]; // @[AXI4Flash.scala 49:37] wire [7:0] in_aw_bits_len = auto_in_aw_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [2:0] in_aw_bits_size = auto_in_aw_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire in_aw_bits_lock = auto_in_aw_bits_lock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -128,16 +109,22 @@ module AXI4Flash( wire [2:0] in_aw_bits_prot = auto_in_aw_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_aw_bits_qos = auto_in_aw_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [63:0] in_w_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 162:16] - wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 159:18] + wire [1:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 161:16] + wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 158:18] wire [2:0] in_ar_bits_size = auto_in_ar_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire in_ar_bits_lock = auto_in_ar_bits_lock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_ar_bits_cache = auto_in_ar_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [2:0] in_ar_bits_prot = auto_in_ar_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_ar_bits_qos = auto_in_ar_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 164:16] - wire [63:0] in_r_bits_data = {rdata_1,rdata_0}; // @[AXI4Flash.scala 34:29] - wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 139:18] + wire [1:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 163:16] + wire [63:0] in_r_bits_data = flash_data; // @[Nodes.scala 1210:84 AXI4Flash.scala 56:20] + wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 138:18] + FlashHelper flash ( // @[AXI4Flash.scala 51:23] + .clk(flash_clk), + .ren(flash_ren), + .data(flash_data), + .addr(flash_addr) + ); assign auto_in_aw_ready = in_aw_ready; // @[LazyModule.scala 309:16] assign auto_in_w_ready = in_w_ready; // @[LazyModule.scala 309:16] assign auto_in_b_valid = in_b_valid; // @[LazyModule.scala 309:16] @@ -149,18 +136,21 @@ module AXI4Flash( assign auto_in_r_bits_data = in_r_bits_data; // @[LazyModule.scala 309:16] assign auto_in_r_bits_resp = in_b_bits_resp; // @[LazyModule.scala 309:16] assign auto_in_r_bits_last = in_r_bits_last; // @[LazyModule.scala 309:16] + assign flash_clk = clock; // @[AXI4Flash.scala 52:18] + assign flash_ren = in_ar_ready & in_ar_valid; // @[Decoupled.scala 40:37] + assign flash_addr = {16'h0,lo_1}; // @[Cat.scala 30:58] always @(posedge clock) begin - if (reset) begin // @[AXI4SlaveModule.scala 80:22] - state <= 2'h0; // @[AXI4SlaveModule.scala 80:22] + if (reset) begin // @[AXI4SlaveModule.scala 79:22] + state <= 2'h0; // @[AXI4SlaveModule.scala 79:22] end else if (_T_15) begin // @[Conditional.scala 40:58] - if (_T_1) begin // @[AXI4SlaveModule.scala 87:25] - state <= 2'h2; // @[AXI4SlaveModule.scala 88:15] - end else if (_T) begin // @[AXI4SlaveModule.scala 84:25] - state <= 2'h1; // @[AXI4SlaveModule.scala 85:15] + if (_T_1) begin // @[AXI4SlaveModule.scala 86:25] + state <= 2'h2; // @[AXI4SlaveModule.scala 87:15] + end else if (_T) begin // @[AXI4SlaveModule.scala 83:25] + state <= 2'h1; // @[AXI4SlaveModule.scala 84:15] end end else if (_T_18) begin // @[Conditional.scala 39:67] - if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 92:42] - state <= 2'h0; // @[AXI4SlaveModule.scala 93:15] + if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 91:42] + state <= 2'h0; // @[AXI4SlaveModule.scala 92:15] end end else if (_T_21) begin // @[Conditional.scala 39:67] state <= _GEN_3; @@ -169,9 +159,9 @@ module AXI4Flash( end if (reset) begin // @[Counter.scala 60:40] value <= 8'h0; // @[Counter.scala 60:40] - end else if (_T_4) begin // @[AXI4SlaveModule.scala 120:23] - if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 122:28] - value <= 8'h0; // @[AXI4SlaveModule.scala 123:17] + end else if (_T_4) begin // @[AXI4SlaveModule.scala 119:23] + if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 121:28] + value <= 8'h0; // @[AXI4SlaveModule.scala 122:17] end else begin value <= _value_T_1; // @[Counter.scala 76:15] end @@ -198,70 +188,37 @@ module AXI4Flash( `endif if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin $fwrite(32'h80000002, - "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:72 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" - ); // @[AXI4SlaveModule.scala 72:11] + "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:71 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" + ); // @[AXI4SlaveModule.scala 71:11] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 72:11] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin $fwrite(32'h80000002, - "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:75 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" - ); // @[AXI4SlaveModule.scala 75:11] + "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:74 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" + ); // @[AXI4SlaveModule.scala 74:11] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 75:11] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T & ~(_T_57 | reset)) begin - $fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:127 assert(\n"); // @[AXI4SlaveModule.scala 127:13] + $fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:126 assert(\n"); // @[AXI4SlaveModule.scala 126:13] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS - `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T & ~(_T_57 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 127:13] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS end // Register and memory initialization `ifdef RANDOMIZE_GARBAGE_ASSIGN @@ -319,3 +276,4 @@ end // initial `endif `endif // SYNTHESIS endmodule + diff --git a/vcs/testbench/SimMMIO/AXI4IntrGenerator.v b/vcs/testbench/SimMMIO/AXI4IntrGenerator.v new file mode 100644 index 0000000..2fd1193 --- /dev/null +++ b/vcs/testbench/SimMMIO/AXI4IntrGenerator.v @@ -0,0 +1,374 @@ +module AXI4IntrGenerator( + input clock, + input reset, + output auto_in_aw_ready, + input auto_in_aw_valid, + input [1:0] auto_in_aw_bits_id, + input [30:0] auto_in_aw_bits_addr, + input [7:0] auto_in_aw_bits_len, + input [2:0] auto_in_aw_bits_size, + input [1:0] auto_in_aw_bits_burst, + input auto_in_aw_bits_lock, + input [3:0] auto_in_aw_bits_cache, + input [2:0] auto_in_aw_bits_prot, + input [3:0] auto_in_aw_bits_qos, + output auto_in_w_ready, + input auto_in_w_valid, + input [63:0] auto_in_w_bits_data, + input [7:0] auto_in_w_bits_strb, + input auto_in_w_bits_last, + input auto_in_b_ready, + output auto_in_b_valid, + output [1:0] auto_in_b_bits_id, + output [1:0] auto_in_b_bits_resp, + output auto_in_ar_ready, + input auto_in_ar_valid, + input [1:0] auto_in_ar_bits_id, + input [30:0] auto_in_ar_bits_addr, + input [7:0] auto_in_ar_bits_len, + input [2:0] auto_in_ar_bits_size, + input [1:0] auto_in_ar_bits_burst, + input auto_in_ar_bits_lock, + input [3:0] auto_in_ar_bits_cache, + input [2:0] auto_in_ar_bits_prot, + input [3:0] auto_in_ar_bits_qos, + input auto_in_r_ready, + output auto_in_r_valid, + output [1:0] auto_in_r_bits_id, + output [63:0] auto_in_r_bits_data, + output [1:0] auto_in_r_bits_resp, + output auto_in_r_bits_last, + output [255:0] io_extra_intrVec +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; +`endif // RANDOMIZE_REG_INIT + reg [1:0] state; // @[AXI4SlaveModule.scala 79:22] + wire _T_61 = state == 2'h0; // @[AXI4SlaveModule.scala 137:24] + wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 137:24] + wire in_ar_valid = auto_in_ar_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire _T = in_ar_ready & in_ar_valid; // @[Decoupled.scala 40:37] + wire in_aw_ready = _T_61 & ~in_ar_valid; // @[AXI4SlaveModule.scala 155:35] + wire in_aw_valid = auto_in_aw_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire _T_1 = in_aw_ready & in_aw_valid; // @[Decoupled.scala 40:37] + wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 156:23] + wire in_w_valid = auto_in_w_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire _T_2 = in_w_ready & in_w_valid; // @[Decoupled.scala 40:37] + wire in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 159:22] + wire _T_3 = in_b_ready & in_b_valid; // @[Decoupled.scala 40:37] + wire in_r_ready = auto_in_r_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 139:23] + wire _T_4 = in_r_ready & in_r_valid; // @[Decoupled.scala 40:37] + wire [1:0] in_aw_bits_burst = auto_in_aw_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [1:0] in_ar_bits_burst = auto_in_ar_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire _T_15 = 2'h0 == state; // @[Conditional.scala 37:30] + wire _T_18 = 2'h1 == state; // @[Conditional.scala 37:30] + reg [7:0] value; // @[Counter.scala 60:40] + wire [7:0] in_ar_bits_len = auto_in_ar_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + reg [7:0] r; // @[Reg.scala 27:20] + wire [7:0] _T_43 = _T ? in_ar_bits_len : r; // @[Hold.scala 7:48] + wire in_r_bits_last = value == _T_43; // @[AXI4SlaveModule.scala 117:32] + wire _T_21 = 2'h2 == state; // @[Conditional.scala 37:30] + wire in_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 96:42 AXI4SlaveModule.scala 97:15 AXI4SlaveModule.scala 79:22] + wire _T_24 = 2'h3 == state; // @[Conditional.scala 37:30] + wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 101:24 AXI4SlaveModule.scala 102:15 AXI4SlaveModule.scala 79:22] + wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 79:22] + wire [7:0] in_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + reg [30:0] r_1; // @[Reg.scala 27:20] + wire [30:0] in_ar_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [30:0] _GEN_10 = _T ? in_ar_bits_addr : r_1; // @[Reg.scala 28:19 Reg.scala 28:23 Reg.scala 27:20] + wire [7:0] _value_T_1 = value + 8'h1; // @[Counter.scala 76:24] + wire _T_50 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 128:26] + wire _T_51 = in_ar_bits_len == 8'h0 | _T_50; // @[AXI4SlaveModule.scala 127:32] + wire _T_52 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 129:26] + wire _T_53 = _T_51 | _T_52; // @[AXI4SlaveModule.scala 128:34] + wire _T_54 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 130:26] + wire _T_55 = _T_53 | _T_54; // @[AXI4SlaveModule.scala 129:34] + wire _T_56 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 131:26] + wire _T_57 = _T_55 | _T_56; // @[AXI4SlaveModule.scala 130:34] + reg [30:0] r_2; // @[Reg.scala 27:20] + wire [30:0] in_aw_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [30:0] _GEN_13 = _T_1 ? in_aw_bits_addr : r_2; // @[Reg.scala 28:19 Reg.scala 28:23 Reg.scala 27:20] + reg [1:0] r_3; // @[Reg.scala 15:16] + wire [1:0] in_aw_bits_id = auto_in_aw_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + reg [1:0] r_5; // @[Reg.scala 15:16] + wire [1:0] in_ar_bits_id = auto_in_ar_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + reg [31:0] intrReg_0; // @[AXI4IntrGenerator.scala 23:26] + reg [31:0] intrReg_1; // @[AXI4IntrGenerator.scala 23:26] + reg [31:0] intrReg_2; // @[AXI4IntrGenerator.scala 23:26] + reg [31:0] intrReg_3; // @[AXI4IntrGenerator.scala 23:26] + reg [31:0] intrReg_4; // @[AXI4IntrGenerator.scala 23:26] + reg [31:0] intrReg_5; // @[AXI4IntrGenerator.scala 23:26] + reg [31:0] intrReg_6; // @[AXI4IntrGenerator.scala 23:26] + reg [31:0] intrReg_7; // @[AXI4IntrGenerator.scala 23:26] + wire [127:0] lo_1 = {intrReg_3,intrReg_2,intrReg_1,intrReg_0}; // @[Cat.scala 30:58] + wire [127:0] hi_1 = {intrReg_7,intrReg_6,intrReg_5,intrReg_4}; // @[Cat.scala 30:58] + wire [63:0] in_w_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [31:0] _GEN_35 = 3'h1 == _GEN_10[2:0] ? intrReg_1 : intrReg_0; // @[AXI4IntrGenerator.scala 30:20 AXI4IntrGenerator.scala 30:20] + wire [31:0] _GEN_36 = 3'h2 == _GEN_10[2:0] ? intrReg_2 : _GEN_35; // @[AXI4IntrGenerator.scala 30:20 AXI4IntrGenerator.scala 30:20] + wire [31:0] _GEN_37 = 3'h3 == _GEN_10[2:0] ? intrReg_3 : _GEN_36; // @[AXI4IntrGenerator.scala 30:20 AXI4IntrGenerator.scala 30:20] + wire [31:0] _GEN_38 = 3'h4 == _GEN_10[2:0] ? intrReg_4 : _GEN_37; // @[AXI4IntrGenerator.scala 30:20 AXI4IntrGenerator.scala 30:20] + wire [31:0] _GEN_39 = 3'h5 == _GEN_10[2:0] ? intrReg_5 : _GEN_38; // @[AXI4IntrGenerator.scala 30:20 AXI4IntrGenerator.scala 30:20] + wire [31:0] _GEN_40 = 3'h6 == _GEN_10[2:0] ? intrReg_6 : _GEN_39; // @[AXI4IntrGenerator.scala 30:20 AXI4IntrGenerator.scala 30:20] + wire [31:0] _GEN_41 = 3'h7 == _GEN_10[2:0] ? intrReg_7 : _GEN_40; // @[AXI4IntrGenerator.scala 30:20 AXI4IntrGenerator.scala 30:20] + wire [7:0] in_aw_bits_len = auto_in_aw_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [2:0] in_aw_bits_size = auto_in_aw_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire in_aw_bits_lock = auto_in_aw_bits_lock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [3:0] in_aw_bits_cache = auto_in_aw_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [2:0] in_aw_bits_prot = auto_in_aw_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [3:0] in_aw_bits_qos = auto_in_aw_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [1:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 161:16] + wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 158:18] + wire [2:0] in_ar_bits_size = auto_in_ar_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire in_ar_bits_lock = auto_in_ar_bits_lock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [3:0] in_ar_bits_cache = auto_in_ar_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [2:0] in_ar_bits_prot = auto_in_ar_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [3:0] in_ar_bits_qos = auto_in_ar_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + wire [1:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 163:16] + wire [63:0] in_r_bits_data = {{32'd0}, _GEN_41}; // @[Nodes.scala 1210:84 AXI4IntrGenerator.scala 30:20] + wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 138:18] + assign auto_in_aw_ready = in_aw_ready; // @[LazyModule.scala 309:16] + assign auto_in_w_ready = in_w_ready; // @[LazyModule.scala 309:16] + assign auto_in_b_valid = in_b_valid; // @[LazyModule.scala 309:16] + assign auto_in_b_bits_id = in_b_bits_id; // @[LazyModule.scala 309:16] + assign auto_in_b_bits_resp = in_b_bits_resp; // @[LazyModule.scala 309:16] + assign auto_in_ar_ready = in_ar_ready; // @[LazyModule.scala 309:16] + assign auto_in_r_valid = in_r_valid; // @[LazyModule.scala 309:16] + assign auto_in_r_bits_id = in_r_bits_id; // @[LazyModule.scala 309:16] + assign auto_in_r_bits_data = in_r_bits_data; // @[LazyModule.scala 309:16] + assign auto_in_r_bits_resp = in_b_bits_resp; // @[LazyModule.scala 309:16] + assign auto_in_r_bits_last = in_r_bits_last; // @[LazyModule.scala 309:16] + assign io_extra_intrVec = {hi_1,lo_1}; // @[Cat.scala 30:58] + always @(posedge clock) begin + if (reset) begin // @[AXI4SlaveModule.scala 79:22] + state <= 2'h0; // @[AXI4SlaveModule.scala 79:22] + end else if (_T_15) begin // @[Conditional.scala 40:58] + if (_T_1) begin // @[AXI4SlaveModule.scala 86:25] + state <= 2'h2; // @[AXI4SlaveModule.scala 87:15] + end else if (_T) begin // @[AXI4SlaveModule.scala 83:25] + state <= 2'h1; // @[AXI4SlaveModule.scala 84:15] + end + end else if (_T_18) begin // @[Conditional.scala 39:67] + if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 91:42] + state <= 2'h0; // @[AXI4SlaveModule.scala 92:15] + end + end else if (_T_21) begin // @[Conditional.scala 39:67] + state <= _GEN_3; + end else begin + state <= _GEN_5; + end + if (reset) begin // @[Counter.scala 60:40] + value <= 8'h0; // @[Counter.scala 60:40] + end else if (_T_4) begin // @[AXI4SlaveModule.scala 119:23] + if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 121:28] + value <= 8'h0; // @[AXI4SlaveModule.scala 122:17] + end else begin + value <= _value_T_1; // @[Counter.scala 76:15] + end + end + if (reset) begin // @[Reg.scala 27:20] + r <= 8'h0; // @[Reg.scala 27:20] + end else if (_T) begin // @[Hold.scala 7:48] + r <= in_ar_bits_len; + end + if (reset) begin // @[Reg.scala 27:20] + r_1 <= 31'h0; // @[Reg.scala 27:20] + end else if (_T) begin // @[Reg.scala 28:19] + r_1 <= in_ar_bits_addr; // @[Reg.scala 28:23] + end + if (reset) begin // @[Reg.scala 27:20] + r_2 <= 31'h0; // @[Reg.scala 27:20] + end else if (_T_1) begin // @[Reg.scala 28:19] + r_2 <= in_aw_bits_addr; // @[Reg.scala 28:23] + end + if (_T_1) begin // @[Reg.scala 16:19] + r_3 <= in_aw_bits_id; // @[Reg.scala 16:23] + end + if (_T) begin // @[Reg.scala 16:19] + r_5 <= in_ar_bits_id; // @[Reg.scala 16:23] + end + if (reset) begin // @[AXI4IntrGenerator.scala 23:26] + intrReg_0 <= 32'h0; // @[AXI4IntrGenerator.scala 23:26] + end else if (_T_2) begin // @[AXI4IntrGenerator.scala 26:24] + if (3'h0 == _GEN_13[4:2]) begin // @[AXI4IntrGenerator.scala 27:28] + intrReg_0 <= in_w_bits_data[31:0]; // @[AXI4IntrGenerator.scala 27:28] + end + end + if (reset) begin // @[AXI4IntrGenerator.scala 23:26] + intrReg_1 <= 32'h0; // @[AXI4IntrGenerator.scala 23:26] + end else if (_T_2) begin // @[AXI4IntrGenerator.scala 26:24] + if (3'h1 == _GEN_13[4:2]) begin // @[AXI4IntrGenerator.scala 27:28] + intrReg_1 <= in_w_bits_data[31:0]; // @[AXI4IntrGenerator.scala 27:28] + end + end + if (reset) begin // @[AXI4IntrGenerator.scala 23:26] + intrReg_2 <= 32'h0; // @[AXI4IntrGenerator.scala 23:26] + end else if (_T_2) begin // @[AXI4IntrGenerator.scala 26:24] + if (3'h2 == _GEN_13[4:2]) begin // @[AXI4IntrGenerator.scala 27:28] + intrReg_2 <= in_w_bits_data[31:0]; // @[AXI4IntrGenerator.scala 27:28] + end + end + if (reset) begin // @[AXI4IntrGenerator.scala 23:26] + intrReg_3 <= 32'h0; // @[AXI4IntrGenerator.scala 23:26] + end else if (_T_2) begin // @[AXI4IntrGenerator.scala 26:24] + if (3'h3 == _GEN_13[4:2]) begin // @[AXI4IntrGenerator.scala 27:28] + intrReg_3 <= in_w_bits_data[31:0]; // @[AXI4IntrGenerator.scala 27:28] + end + end + if (reset) begin // @[AXI4IntrGenerator.scala 23:26] + intrReg_4 <= 32'h0; // @[AXI4IntrGenerator.scala 23:26] + end else if (_T_2) begin // @[AXI4IntrGenerator.scala 26:24] + if (3'h4 == _GEN_13[4:2]) begin // @[AXI4IntrGenerator.scala 27:28] + intrReg_4 <= in_w_bits_data[31:0]; // @[AXI4IntrGenerator.scala 27:28] + end + end + if (reset) begin // @[AXI4IntrGenerator.scala 23:26] + intrReg_5 <= 32'h0; // @[AXI4IntrGenerator.scala 23:26] + end else if (_T_2) begin // @[AXI4IntrGenerator.scala 26:24] + if (3'h5 == _GEN_13[4:2]) begin // @[AXI4IntrGenerator.scala 27:28] + intrReg_5 <= in_w_bits_data[31:0]; // @[AXI4IntrGenerator.scala 27:28] + end + end + if (reset) begin // @[AXI4IntrGenerator.scala 23:26] + intrReg_6 <= 32'h0; // @[AXI4IntrGenerator.scala 23:26] + end else if (_T_2) begin // @[AXI4IntrGenerator.scala 26:24] + if (3'h6 == _GEN_13[4:2]) begin // @[AXI4IntrGenerator.scala 27:28] + intrReg_6 <= in_w_bits_data[31:0]; // @[AXI4IntrGenerator.scala 27:28] + end + end + if (reset) begin // @[AXI4IntrGenerator.scala 23:26] + intrReg_7 <= 32'h0; // @[AXI4IntrGenerator.scala 23:26] + end else if (_T_2) begin // @[AXI4IntrGenerator.scala 26:24] + if (3'h7 == _GEN_13[4:2]) begin // @[AXI4IntrGenerator.scala 27:28] + intrReg_7 <= in_w_bits_data[31:0]; // @[AXI4IntrGenerator.scala 27:28] + end + end + `ifndef SYNTHESIS + `ifdef PRINTF_COND + if (`PRINTF_COND) begin + `endif + if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin + $fwrite(32'h80000002, + "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:71 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" + ); // @[AXI4SlaveModule.scala 71:11] + end + `ifdef PRINTF_COND + end + `endif + `endif // SYNTHESIS + `ifndef SYNTHESIS + `ifdef PRINTF_COND + if (`PRINTF_COND) begin + `endif + if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin + $fwrite(32'h80000002, + "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:74 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" + ); // @[AXI4SlaveModule.scala 74:11] + end + `ifdef PRINTF_COND + end + `endif + `endif // SYNTHESIS + `ifndef SYNTHESIS + `ifdef PRINTF_COND + if (`PRINTF_COND) begin + `endif + if (_T & ~(_T_57 | reset)) begin + $fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:126 assert(\n"); // @[AXI4SlaveModule.scala 126:13] + end + `ifdef PRINTF_COND + end + `endif + `endif // SYNTHESIS + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + state = _RAND_0[1:0]; + _RAND_1 = {1{`RANDOM}}; + value = _RAND_1[7:0]; + _RAND_2 = {1{`RANDOM}}; + r = _RAND_2[7:0]; + _RAND_3 = {1{`RANDOM}}; + r_1 = _RAND_3[30:0]; + _RAND_4 = {1{`RANDOM}}; + r_2 = _RAND_4[30:0]; + _RAND_5 = {1{`RANDOM}}; + r_3 = _RAND_5[1:0]; + _RAND_6 = {1{`RANDOM}}; + r_5 = _RAND_6[1:0]; + _RAND_7 = {1{`RANDOM}}; + intrReg_0 = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + intrReg_1 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + intrReg_2 = _RAND_9[31:0]; + _RAND_10 = {1{`RANDOM}}; + intrReg_3 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + intrReg_4 = _RAND_11[31:0]; + _RAND_12 = {1{`RANDOM}}; + intrReg_5 = _RAND_12[31:0]; + _RAND_13 = {1{`RANDOM}}; + intrReg_6 = _RAND_13[31:0]; + _RAND_14 = {1{`RANDOM}}; + intrReg_7 = _RAND_14[31:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule + diff --git a/vcs/testbench/SimMMIO/AXI4RAM_1.v b/vcs/testbench/SimMMIO/AXI4RAM.v similarity index 72% rename from vcs/testbench/SimMMIO/AXI4RAM_1.v rename to vcs/testbench/SimMMIO/AXI4RAM.v index cce1a99..8d47b49 100644 --- a/vcs/testbench/SimMMIO/AXI4RAM_1.v +++ b/vcs/testbench/SimMMIO/AXI4RAM.v @@ -1,4 +1,4 @@ -module AXI4RAM_1( +module AXI4RAM( input clock, input reset, output auto_in_aw_ready, @@ -63,78 +63,78 @@ module AXI4RAM_1( reg [31:0] _RAND_22; reg [31:0] _RAND_23; `endif // RANDOMIZE_REG_INIT - reg [7:0] MEM_0 [0:59999]; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_0_MPORT_1_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_0_MPORT_1_addr; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_0_MPORT_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_0_MPORT_addr; // @[AXI4RAM.scala 67:20] - wire MEM_0_MPORT_mask; // @[AXI4RAM.scala 67:20] - wire MEM_0_MPORT_en; // @[AXI4RAM.scala 67:20] - reg [7:0] MEM_1 [0:59999]; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_1_MPORT_1_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_1_MPORT_1_addr; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_1_MPORT_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_1_MPORT_addr; // @[AXI4RAM.scala 67:20] - wire MEM_1_MPORT_mask; // @[AXI4RAM.scala 67:20] - wire MEM_1_MPORT_en; // @[AXI4RAM.scala 67:20] - reg [7:0] MEM_2 [0:59999]; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_2_MPORT_1_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_2_MPORT_1_addr; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_2_MPORT_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_2_MPORT_addr; // @[AXI4RAM.scala 67:20] - wire MEM_2_MPORT_mask; // @[AXI4RAM.scala 67:20] - wire MEM_2_MPORT_en; // @[AXI4RAM.scala 67:20] - reg [7:0] MEM_3 [0:59999]; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_3_MPORT_1_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_3_MPORT_1_addr; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_3_MPORT_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_3_MPORT_addr; // @[AXI4RAM.scala 67:20] - wire MEM_3_MPORT_mask; // @[AXI4RAM.scala 67:20] - wire MEM_3_MPORT_en; // @[AXI4RAM.scala 67:20] - reg [7:0] MEM_4 [0:59999]; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_4_MPORT_1_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_4_MPORT_1_addr; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_4_MPORT_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_4_MPORT_addr; // @[AXI4RAM.scala 67:20] - wire MEM_4_MPORT_mask; // @[AXI4RAM.scala 67:20] - wire MEM_4_MPORT_en; // @[AXI4RAM.scala 67:20] - reg [7:0] MEM_5 [0:59999]; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_5_MPORT_1_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_5_MPORT_1_addr; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_5_MPORT_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_5_MPORT_addr; // @[AXI4RAM.scala 67:20] - wire MEM_5_MPORT_mask; // @[AXI4RAM.scala 67:20] - wire MEM_5_MPORT_en; // @[AXI4RAM.scala 67:20] - reg [7:0] MEM_6 [0:59999]; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_6_MPORT_1_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_6_MPORT_1_addr; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_6_MPORT_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_6_MPORT_addr; // @[AXI4RAM.scala 67:20] - wire MEM_6_MPORT_mask; // @[AXI4RAM.scala 67:20] - wire MEM_6_MPORT_en; // @[AXI4RAM.scala 67:20] - reg [7:0] MEM_7 [0:59999]; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_7_MPORT_1_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_7_MPORT_1_addr; // @[AXI4RAM.scala 67:20] - wire [7:0] MEM_7_MPORT_data; // @[AXI4RAM.scala 67:20] - wire [15:0] MEM_7_MPORT_addr; // @[AXI4RAM.scala 67:20] - wire MEM_7_MPORT_mask; // @[AXI4RAM.scala 67:20] - wire MEM_7_MPORT_en; // @[AXI4RAM.scala 67:20] - reg [1:0] state; // @[AXI4SlaveModule.scala 80:22] - wire _T_61 = state == 2'h0; // @[AXI4SlaveModule.scala 138:24] - wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 138:24] + reg [7:0] MEM_0 [0:59999]; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_0_MPORT_1_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_0_MPORT_1_addr; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_0_MPORT_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_0_MPORT_addr; // @[AXI4RAM.scala 69:20] + wire MEM_0_MPORT_mask; // @[AXI4RAM.scala 69:20] + wire MEM_0_MPORT_en; // @[AXI4RAM.scala 69:20] + reg [7:0] MEM_1 [0:59999]; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_1_MPORT_1_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_1_MPORT_1_addr; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_1_MPORT_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_1_MPORT_addr; // @[AXI4RAM.scala 69:20] + wire MEM_1_MPORT_mask; // @[AXI4RAM.scala 69:20] + wire MEM_1_MPORT_en; // @[AXI4RAM.scala 69:20] + reg [7:0] MEM_2 [0:59999]; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_2_MPORT_1_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_2_MPORT_1_addr; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_2_MPORT_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_2_MPORT_addr; // @[AXI4RAM.scala 69:20] + wire MEM_2_MPORT_mask; // @[AXI4RAM.scala 69:20] + wire MEM_2_MPORT_en; // @[AXI4RAM.scala 69:20] + reg [7:0] MEM_3 [0:59999]; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_3_MPORT_1_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_3_MPORT_1_addr; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_3_MPORT_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_3_MPORT_addr; // @[AXI4RAM.scala 69:20] + wire MEM_3_MPORT_mask; // @[AXI4RAM.scala 69:20] + wire MEM_3_MPORT_en; // @[AXI4RAM.scala 69:20] + reg [7:0] MEM_4 [0:59999]; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_4_MPORT_1_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_4_MPORT_1_addr; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_4_MPORT_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_4_MPORT_addr; // @[AXI4RAM.scala 69:20] + wire MEM_4_MPORT_mask; // @[AXI4RAM.scala 69:20] + wire MEM_4_MPORT_en; // @[AXI4RAM.scala 69:20] + reg [7:0] MEM_5 [0:59999]; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_5_MPORT_1_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_5_MPORT_1_addr; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_5_MPORT_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_5_MPORT_addr; // @[AXI4RAM.scala 69:20] + wire MEM_5_MPORT_mask; // @[AXI4RAM.scala 69:20] + wire MEM_5_MPORT_en; // @[AXI4RAM.scala 69:20] + reg [7:0] MEM_6 [0:59999]; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_6_MPORT_1_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_6_MPORT_1_addr; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_6_MPORT_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_6_MPORT_addr; // @[AXI4RAM.scala 69:20] + wire MEM_6_MPORT_mask; // @[AXI4RAM.scala 69:20] + wire MEM_6_MPORT_en; // @[AXI4RAM.scala 69:20] + reg [7:0] MEM_7 [0:59999]; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_7_MPORT_1_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_7_MPORT_1_addr; // @[AXI4RAM.scala 69:20] + wire [7:0] MEM_7_MPORT_data; // @[AXI4RAM.scala 69:20] + wire [15:0] MEM_7_MPORT_addr; // @[AXI4RAM.scala 69:20] + wire MEM_7_MPORT_mask; // @[AXI4RAM.scala 69:20] + wire MEM_7_MPORT_en; // @[AXI4RAM.scala 69:20] + reg [1:0] state; // @[AXI4SlaveModule.scala 79:22] + wire _T_61 = state == 2'h0; // @[AXI4SlaveModule.scala 137:24] + wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 137:24] wire in_ar_valid = auto_in_ar_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T = in_ar_ready & in_ar_valid; // @[Decoupled.scala 40:37] - wire in_aw_ready = _T_61 & ~in_ar_valid; // @[AXI4SlaveModule.scala 156:35] + wire in_aw_ready = _T_61 & ~in_ar_valid; // @[AXI4SlaveModule.scala 155:35] wire in_aw_valid = auto_in_aw_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T_1 = in_aw_ready & in_aw_valid; // @[Decoupled.scala 40:37] - wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 157:23] + wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 156:23] wire in_w_valid = auto_in_w_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T_2 = in_w_ready & in_w_valid; // @[Decoupled.scala 40:37] wire in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 160:22] + wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 159:22] wire _T_3 = in_b_ready & in_b_valid; // @[Decoupled.scala 40:37] wire in_r_ready = 1'h1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 140:23] + wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 139:23] wire _T_4 = in_r_ready & in_r_valid; // @[Decoupled.scala 40:37] wire [1:0] in_aw_bits_burst = auto_in_aw_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [1:0] in_ar_bits_burst = auto_in_ar_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -144,26 +144,26 @@ module AXI4RAM_1( wire [7:0] in_ar_bits_len = auto_in_ar_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [7:0] r; // @[Reg.scala 27:20] wire [7:0] _T_43 = _T ? in_ar_bits_len : r; // @[Hold.scala 7:48] - wire in_r_bits_last = value == _T_43; // @[AXI4SlaveModule.scala 118:32] + wire in_r_bits_last = value == _T_43; // @[AXI4SlaveModule.scala 117:32] wire _T_21 = 2'h2 == state; // @[Conditional.scala 37:30] wire in_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 97:42 AXI4SlaveModule.scala 98:15 AXI4SlaveModule.scala 80:22] + wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 96:42 AXI4SlaveModule.scala 97:15 AXI4SlaveModule.scala 79:22] wire _T_24 = 2'h3 == state; // @[Conditional.scala 37:30] - wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 102:24 AXI4SlaveModule.scala 103:15 AXI4SlaveModule.scala 80:22] - wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 80:22] + wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 101:24 AXI4SlaveModule.scala 102:15 AXI4SlaveModule.scala 79:22] + wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 79:22] wire [7:0] in_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [30:0] r_1; // @[Reg.scala 27:20] wire [30:0] in_ar_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [30:0] _GEN_10 = _T ? in_ar_bits_addr : r_1; // @[Reg.scala 28:19 Reg.scala 28:23 Reg.scala 27:20] wire [7:0] _value_T_1 = value + 8'h1; // @[Counter.scala 76:24] - wire _T_50 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 129:26] - wire _T_51 = in_ar_bits_len == 8'h0 | _T_50; // @[AXI4SlaveModule.scala 128:32] - wire _T_52 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 130:26] - wire _T_53 = _T_51 | _T_52; // @[AXI4SlaveModule.scala 129:34] - wire _T_54 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 131:26] - wire _T_55 = _T_53 | _T_54; // @[AXI4SlaveModule.scala 130:34] - wire _T_56 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 132:26] - wire _T_57 = _T_55 | _T_56; // @[AXI4SlaveModule.scala 131:34] + wire _T_50 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 128:26] + wire _T_51 = in_ar_bits_len == 8'h0 | _T_50; // @[AXI4SlaveModule.scala 127:32] + wire _T_52 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 129:26] + wire _T_53 = _T_51 | _T_52; // @[AXI4SlaveModule.scala 128:34] + wire _T_54 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 130:26] + wire _T_55 = _T_53 | _T_54; // @[AXI4SlaveModule.scala 129:34] + wire _T_56 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 131:26] + wire _T_57 = _T_55 | _T_56; // @[AXI4SlaveModule.scala 130:34] reg [7:0] value_1; // @[Counter.scala 60:40] reg [30:0] r_2; // @[Reg.scala 27:20] wire [30:0] in_aw_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -173,12 +173,12 @@ module AXI4RAM_1( wire [1:0] in_aw_bits_id = auto_in_aw_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [1:0] r_5; // @[Reg.scala 15:16] wire [1:0] in_ar_bits_id = auto_in_ar_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [30:0] _T_76 = _GEN_13 - 31'h50000000; // @[AXI4RAM.scala 44:36] - wire [15:0] _GEN_53 = {{8'd0}, value_1}; // @[AXI4RAM.scala 48:29] - wire [15:0] wIdx = _T_76[18:3] + _GEN_53; // @[AXI4RAM.scala 48:29] - wire [30:0] _T_81 = _GEN_10 - 31'h50000000; // @[AXI4RAM.scala 44:36] - wire [15:0] _GEN_54 = {{8'd0}, value}; // @[AXI4RAM.scala 49:29] - wire _T_86 = wIdx < 16'hea60; // @[AXI4RAM.scala 46:34] + wire [30:0] _T_76 = _GEN_13 - 31'h50000000; // @[AXI4RAM.scala 46:36] + wire [15:0] _GEN_53 = {{8'd0}, value_1}; // @[AXI4RAM.scala 50:29] + wire [15:0] wIdx = _T_76[18:3] + _GEN_53; // @[AXI4RAM.scala 50:29] + wire [30:0] _T_81 = _GEN_10 - 31'h50000000; // @[AXI4RAM.scala 46:36] + wire [15:0] _GEN_54 = {{8'd0}, value}; // @[AXI4RAM.scala 51:29] + wire _T_86 = wIdx < 16'hea60; // @[AXI4RAM.scala 48:34] wire [63:0] in_w_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [63:0] rdata = {MEM_7_MPORT_1_data,MEM_6_MPORT_1_data,MEM_5_MPORT_1_data,MEM_4_MPORT_1_data,MEM_3_MPORT_1_data, MEM_2_MPORT_1_data,MEM_1_MPORT_1_data,MEM_0_MPORT_1_data}; // @[Cat.scala 30:58] @@ -188,21 +188,21 @@ module AXI4RAM_1( wire [3:0] in_aw_bits_cache = auto_in_aw_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [2:0] in_aw_bits_prot = auto_in_aw_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_aw_bits_qos = auto_in_aw_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 162:16] - wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 159:18] + wire [1:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 161:16] + wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 158:18] wire [2:0] in_ar_bits_size = auto_in_ar_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire in_ar_bits_lock = auto_in_ar_bits_lock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_ar_bits_cache = auto_in_ar_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [2:0] in_ar_bits_prot = 3'h0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_ar_bits_qos = auto_in_ar_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 164:16] + wire [1:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 163:16] wire [63:0] in_r_bits_data = rdata; // @[Cat.scala 30:58] - wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 139:18] + wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 138:18] assign MEM_0_MPORT_1_addr = _T_81[18:3] + _GEN_54; `ifndef RANDOMIZE_GARBAGE_ASSIGN - assign MEM_0_MPORT_1_data = MEM_0[MEM_0_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_0_MPORT_1_data = MEM_0[MEM_0_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `else - assign MEM_0_MPORT_1_data = MEM_0_MPORT_1_addr >= 16'hea60 ? _RAND_1[7:0] : MEM_0[MEM_0_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_0_MPORT_1_data = MEM_0_MPORT_1_addr >= 16'hea60 ? _RAND_1[7:0] : MEM_0[MEM_0_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `endif // RANDOMIZE_GARBAGE_ASSIGN assign MEM_0_MPORT_data = in_w_bits_data[7:0]; assign MEM_0_MPORT_addr = _T_76[18:3] + _GEN_53; @@ -210,9 +210,9 @@ module AXI4RAM_1( assign MEM_0_MPORT_en = _T_2 & _T_86; assign MEM_1_MPORT_1_addr = _T_81[18:3] + _GEN_54; `ifndef RANDOMIZE_GARBAGE_ASSIGN - assign MEM_1_MPORT_1_data = MEM_1[MEM_1_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_1_MPORT_1_data = MEM_1[MEM_1_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `else - assign MEM_1_MPORT_1_data = MEM_1_MPORT_1_addr >= 16'hea60 ? _RAND_3[7:0] : MEM_1[MEM_1_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_1_MPORT_1_data = MEM_1_MPORT_1_addr >= 16'hea60 ? _RAND_3[7:0] : MEM_1[MEM_1_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `endif // RANDOMIZE_GARBAGE_ASSIGN assign MEM_1_MPORT_data = in_w_bits_data[15:8]; assign MEM_1_MPORT_addr = _T_76[18:3] + _GEN_53; @@ -220,9 +220,9 @@ module AXI4RAM_1( assign MEM_1_MPORT_en = _T_2 & _T_86; assign MEM_2_MPORT_1_addr = _T_81[18:3] + _GEN_54; `ifndef RANDOMIZE_GARBAGE_ASSIGN - assign MEM_2_MPORT_1_data = MEM_2[MEM_2_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_2_MPORT_1_data = MEM_2[MEM_2_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `else - assign MEM_2_MPORT_1_data = MEM_2_MPORT_1_addr >= 16'hea60 ? _RAND_5[7:0] : MEM_2[MEM_2_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_2_MPORT_1_data = MEM_2_MPORT_1_addr >= 16'hea60 ? _RAND_5[7:0] : MEM_2[MEM_2_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `endif // RANDOMIZE_GARBAGE_ASSIGN assign MEM_2_MPORT_data = in_w_bits_data[23:16]; assign MEM_2_MPORT_addr = _T_76[18:3] + _GEN_53; @@ -230,9 +230,9 @@ module AXI4RAM_1( assign MEM_2_MPORT_en = _T_2 & _T_86; assign MEM_3_MPORT_1_addr = _T_81[18:3] + _GEN_54; `ifndef RANDOMIZE_GARBAGE_ASSIGN - assign MEM_3_MPORT_1_data = MEM_3[MEM_3_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_3_MPORT_1_data = MEM_3[MEM_3_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `else - assign MEM_3_MPORT_1_data = MEM_3_MPORT_1_addr >= 16'hea60 ? _RAND_7[7:0] : MEM_3[MEM_3_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_3_MPORT_1_data = MEM_3_MPORT_1_addr >= 16'hea60 ? _RAND_7[7:0] : MEM_3[MEM_3_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `endif // RANDOMIZE_GARBAGE_ASSIGN assign MEM_3_MPORT_data = in_w_bits_data[31:24]; assign MEM_3_MPORT_addr = _T_76[18:3] + _GEN_53; @@ -240,9 +240,9 @@ module AXI4RAM_1( assign MEM_3_MPORT_en = _T_2 & _T_86; assign MEM_4_MPORT_1_addr = _T_81[18:3] + _GEN_54; `ifndef RANDOMIZE_GARBAGE_ASSIGN - assign MEM_4_MPORT_1_data = MEM_4[MEM_4_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_4_MPORT_1_data = MEM_4[MEM_4_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `else - assign MEM_4_MPORT_1_data = MEM_4_MPORT_1_addr >= 16'hea60 ? _RAND_9[7:0] : MEM_4[MEM_4_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_4_MPORT_1_data = MEM_4_MPORT_1_addr >= 16'hea60 ? _RAND_9[7:0] : MEM_4[MEM_4_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `endif // RANDOMIZE_GARBAGE_ASSIGN assign MEM_4_MPORT_data = in_w_bits_data[39:32]; assign MEM_4_MPORT_addr = _T_76[18:3] + _GEN_53; @@ -250,9 +250,9 @@ module AXI4RAM_1( assign MEM_4_MPORT_en = _T_2 & _T_86; assign MEM_5_MPORT_1_addr = _T_81[18:3] + _GEN_54; `ifndef RANDOMIZE_GARBAGE_ASSIGN - assign MEM_5_MPORT_1_data = MEM_5[MEM_5_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_5_MPORT_1_data = MEM_5[MEM_5_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `else - assign MEM_5_MPORT_1_data = MEM_5_MPORT_1_addr >= 16'hea60 ? _RAND_11[7:0] : MEM_5[MEM_5_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_5_MPORT_1_data = MEM_5_MPORT_1_addr >= 16'hea60 ? _RAND_11[7:0] : MEM_5[MEM_5_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `endif // RANDOMIZE_GARBAGE_ASSIGN assign MEM_5_MPORT_data = in_w_bits_data[47:40]; assign MEM_5_MPORT_addr = _T_76[18:3] + _GEN_53; @@ -260,9 +260,9 @@ module AXI4RAM_1( assign MEM_5_MPORT_en = _T_2 & _T_86; assign MEM_6_MPORT_1_addr = _T_81[18:3] + _GEN_54; `ifndef RANDOMIZE_GARBAGE_ASSIGN - assign MEM_6_MPORT_1_data = MEM_6[MEM_6_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_6_MPORT_1_data = MEM_6[MEM_6_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `else - assign MEM_6_MPORT_1_data = MEM_6_MPORT_1_addr >= 16'hea60 ? _RAND_13[7:0] : MEM_6[MEM_6_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_6_MPORT_1_data = MEM_6_MPORT_1_addr >= 16'hea60 ? _RAND_13[7:0] : MEM_6[MEM_6_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `endif // RANDOMIZE_GARBAGE_ASSIGN assign MEM_6_MPORT_data = in_w_bits_data[55:48]; assign MEM_6_MPORT_addr = _T_76[18:3] + _GEN_53; @@ -270,9 +270,9 @@ module AXI4RAM_1( assign MEM_6_MPORT_en = _T_2 & _T_86; assign MEM_7_MPORT_1_addr = _T_81[18:3] + _GEN_54; `ifndef RANDOMIZE_GARBAGE_ASSIGN - assign MEM_7_MPORT_1_data = MEM_7[MEM_7_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_7_MPORT_1_data = MEM_7[MEM_7_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `else - assign MEM_7_MPORT_1_data = MEM_7_MPORT_1_addr >= 16'hea60 ? _RAND_15[7:0] : MEM_7[MEM_7_MPORT_1_addr]; // @[AXI4RAM.scala 67:20] + assign MEM_7_MPORT_1_data = MEM_7_MPORT_1_addr >= 16'hea60 ? _RAND_15[7:0] : MEM_7[MEM_7_MPORT_1_addr]; // @[AXI4RAM.scala 69:20] `endif // RANDOMIZE_GARBAGE_ASSIGN assign MEM_7_MPORT_data = in_w_bits_data[63:56]; assign MEM_7_MPORT_addr = _T_76[18:3] + _GEN_53; @@ -287,40 +287,40 @@ module AXI4RAM_1( assign auto_in_r_bits_last = in_r_bits_last; // @[LazyModule.scala 309:16] always @(posedge clock) begin if(MEM_0_MPORT_en & MEM_0_MPORT_mask) begin - MEM_0[MEM_0_MPORT_addr] <= MEM_0_MPORT_data; // @[AXI4RAM.scala 67:20] + MEM_0[MEM_0_MPORT_addr] <= MEM_0_MPORT_data; // @[AXI4RAM.scala 69:20] end if(MEM_1_MPORT_en & MEM_1_MPORT_mask) begin - MEM_1[MEM_1_MPORT_addr] <= MEM_1_MPORT_data; // @[AXI4RAM.scala 67:20] + MEM_1[MEM_1_MPORT_addr] <= MEM_1_MPORT_data; // @[AXI4RAM.scala 69:20] end if(MEM_2_MPORT_en & MEM_2_MPORT_mask) begin - MEM_2[MEM_2_MPORT_addr] <= MEM_2_MPORT_data; // @[AXI4RAM.scala 67:20] + MEM_2[MEM_2_MPORT_addr] <= MEM_2_MPORT_data; // @[AXI4RAM.scala 69:20] end if(MEM_3_MPORT_en & MEM_3_MPORT_mask) begin - MEM_3[MEM_3_MPORT_addr] <= MEM_3_MPORT_data; // @[AXI4RAM.scala 67:20] + MEM_3[MEM_3_MPORT_addr] <= MEM_3_MPORT_data; // @[AXI4RAM.scala 69:20] end if(MEM_4_MPORT_en & MEM_4_MPORT_mask) begin - MEM_4[MEM_4_MPORT_addr] <= MEM_4_MPORT_data; // @[AXI4RAM.scala 67:20] + MEM_4[MEM_4_MPORT_addr] <= MEM_4_MPORT_data; // @[AXI4RAM.scala 69:20] end if(MEM_5_MPORT_en & MEM_5_MPORT_mask) begin - MEM_5[MEM_5_MPORT_addr] <= MEM_5_MPORT_data; // @[AXI4RAM.scala 67:20] + MEM_5[MEM_5_MPORT_addr] <= MEM_5_MPORT_data; // @[AXI4RAM.scala 69:20] end if(MEM_6_MPORT_en & MEM_6_MPORT_mask) begin - MEM_6[MEM_6_MPORT_addr] <= MEM_6_MPORT_data; // @[AXI4RAM.scala 67:20] + MEM_6[MEM_6_MPORT_addr] <= MEM_6_MPORT_data; // @[AXI4RAM.scala 69:20] end if(MEM_7_MPORT_en & MEM_7_MPORT_mask) begin - MEM_7[MEM_7_MPORT_addr] <= MEM_7_MPORT_data; // @[AXI4RAM.scala 67:20] + MEM_7[MEM_7_MPORT_addr] <= MEM_7_MPORT_data; // @[AXI4RAM.scala 69:20] end - if (reset) begin // @[AXI4SlaveModule.scala 80:22] - state <= 2'h0; // @[AXI4SlaveModule.scala 80:22] + if (reset) begin // @[AXI4SlaveModule.scala 79:22] + state <= 2'h0; // @[AXI4SlaveModule.scala 79:22] end else if (_T_15) begin // @[Conditional.scala 40:58] - if (_T_1) begin // @[AXI4SlaveModule.scala 87:25] - state <= 2'h2; // @[AXI4SlaveModule.scala 88:15] - end else if (_T) begin // @[AXI4SlaveModule.scala 84:25] - state <= 2'h1; // @[AXI4SlaveModule.scala 85:15] + if (_T_1) begin // @[AXI4SlaveModule.scala 86:25] + state <= 2'h2; // @[AXI4SlaveModule.scala 87:15] + end else if (_T) begin // @[AXI4SlaveModule.scala 83:25] + state <= 2'h1; // @[AXI4SlaveModule.scala 84:15] end end else if (_T_18) begin // @[Conditional.scala 39:67] - if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 92:42] - state <= 2'h0; // @[AXI4SlaveModule.scala 93:15] + if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 91:42] + state <= 2'h0; // @[AXI4SlaveModule.scala 92:15] end end else if (_T_21) begin // @[Conditional.scala 39:67] state <= _GEN_3; @@ -329,9 +329,9 @@ module AXI4RAM_1( end if (reset) begin // @[Counter.scala 60:40] value <= 8'h0; // @[Counter.scala 60:40] - end else if (_T_4) begin // @[AXI4SlaveModule.scala 120:23] - if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 122:28] - value <= 8'h0; // @[AXI4SlaveModule.scala 123:17] + end else if (_T_4) begin // @[AXI4SlaveModule.scala 119:23] + if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 121:28] + value <= 8'h0; // @[AXI4SlaveModule.scala 122:17] end else begin value <= _value_T_1; // @[Counter.scala 76:15] end @@ -348,9 +348,9 @@ module AXI4RAM_1( end if (reset) begin // @[Counter.scala 60:40] value_1 <= 8'h0; // @[Counter.scala 60:40] - end else if (_T_2) begin // @[AXI4SlaveModule.scala 147:23] - if (in_w_bits_last) begin // @[AXI4SlaveModule.scala 149:28] - value_1 <= 8'h0; // @[AXI4SlaveModule.scala 150:17] + end else if (_T_2) begin // @[AXI4SlaveModule.scala 146:23] + if (in_w_bits_last) begin // @[AXI4SlaveModule.scala 148:28] + value_1 <= 8'h0; // @[AXI4SlaveModule.scala 149:17] end else begin value_1 <= _value_T_3; // @[Counter.scala 76:15] end @@ -372,70 +372,37 @@ module AXI4RAM_1( `endif if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin $fwrite(32'h80000002, - "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:72 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" - ); // @[AXI4SlaveModule.scala 72:11] + "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:71 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" + ); // @[AXI4SlaveModule.scala 71:11] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 72:11] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin $fwrite(32'h80000002, - "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:75 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" - ); // @[AXI4SlaveModule.scala 75:11] + "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:74 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" + ); // @[AXI4SlaveModule.scala 74:11] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 75:11] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T & ~(_T_57 | reset)) begin - $fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:127 assert(\n"); // @[AXI4SlaveModule.scala 127:13] + $fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:126 assert(\n"); // @[AXI4SlaveModule.scala 126:13] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS - `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T & ~(_T_57 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 127:13] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS end // Register and memory initialization `ifdef RANDOMIZE_GARBAGE_ASSIGN @@ -533,3 +500,4 @@ end // initial `endif `endif // SYNTHESIS endmodule + diff --git a/vcs/testbench/SimMMIO/AXI4UART.v b/vcs/testbench/SimMMIO/AXI4UART.v index 7aafce8..f66096a 100644 --- a/vcs/testbench/SimMMIO/AXI4UART.v +++ b/vcs/testbench/SimMMIO/AXI4UART.v @@ -55,22 +55,22 @@ module AXI4UART( reg [31:0] _RAND_8; reg [31:0] _RAND_9; `endif // RANDOMIZE_REG_INIT - reg [1:0] state; // @[AXI4SlaveModule.scala 80:22] - wire _T_61 = state == 2'h0; // @[AXI4SlaveModule.scala 138:24] - wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 138:24] + reg [1:0] state; // @[AXI4SlaveModule.scala 79:22] + wire _T_61 = state == 2'h0; // @[AXI4SlaveModule.scala 137:24] + wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 137:24] wire in_ar_valid = auto_in_ar_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T = in_ar_ready & in_ar_valid; // @[Decoupled.scala 40:37] - wire in_aw_ready = _T_61 & ~in_ar_valid; // @[AXI4SlaveModule.scala 156:35] + wire in_aw_ready = _T_61 & ~in_ar_valid; // @[AXI4SlaveModule.scala 155:35] wire in_aw_valid = auto_in_aw_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T_1 = in_aw_ready & in_aw_valid; // @[Decoupled.scala 40:37] - wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 157:23] + wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 156:23] wire in_w_valid = auto_in_w_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T_2 = in_w_ready & in_w_valid; // @[Decoupled.scala 40:37] wire in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 160:22] + wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 159:22] wire _T_3 = in_b_ready & in_b_valid; // @[Decoupled.scala 40:37] wire in_r_ready = auto_in_r_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 140:23] + wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 139:23] wire _T_4 = in_r_ready & in_r_valid; // @[Decoupled.scala 40:37] wire [1:0] in_aw_bits_burst = auto_in_aw_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [1:0] in_ar_bits_burst = auto_in_ar_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -80,26 +80,26 @@ module AXI4UART( wire [7:0] in_ar_bits_len = auto_in_ar_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [7:0] r; // @[Reg.scala 27:20] wire [7:0] _T_43 = _T ? in_ar_bits_len : r; // @[Hold.scala 7:48] - wire in_r_bits_last = value == _T_43; // @[AXI4SlaveModule.scala 118:32] + wire in_r_bits_last = value == _T_43; // @[AXI4SlaveModule.scala 117:32] wire _T_21 = 2'h2 == state; // @[Conditional.scala 37:30] wire in_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 97:42 AXI4SlaveModule.scala 98:15 AXI4SlaveModule.scala 80:22] + wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 96:42 AXI4SlaveModule.scala 97:15 AXI4SlaveModule.scala 79:22] wire _T_24 = 2'h3 == state; // @[Conditional.scala 37:30] - wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 102:24 AXI4SlaveModule.scala 103:15 AXI4SlaveModule.scala 80:22] - wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 80:22] + wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 101:24 AXI4SlaveModule.scala 102:15 AXI4SlaveModule.scala 79:22] + wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 79:22] wire [7:0] in_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [30:0] r_1; // @[Reg.scala 27:20] wire [30:0] in_ar_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [30:0] _GEN_10 = _T ? in_ar_bits_addr : r_1; // @[Reg.scala 28:19 Reg.scala 28:23 Reg.scala 27:20] wire [7:0] _value_T_1 = value + 8'h1; // @[Counter.scala 76:24] - wire _T_50 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 129:26] - wire _T_51 = in_ar_bits_len == 8'h0 | _T_50; // @[AXI4SlaveModule.scala 128:32] - wire _T_52 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 130:26] - wire _T_53 = _T_51 | _T_52; // @[AXI4SlaveModule.scala 129:34] - wire _T_54 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 131:26] - wire _T_55 = _T_53 | _T_54; // @[AXI4SlaveModule.scala 130:34] - wire _T_56 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 132:26] - wire _T_57 = _T_55 | _T_56; // @[AXI4SlaveModule.scala 131:34] + wire _T_50 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 128:26] + wire _T_51 = in_ar_bits_len == 8'h0 | _T_50; // @[AXI4SlaveModule.scala 127:32] + wire _T_52 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 129:26] + wire _T_53 = _T_51 | _T_52; // @[AXI4SlaveModule.scala 128:34] + wire _T_54 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 130:26] + wire _T_55 = _T_53 | _T_54; // @[AXI4SlaveModule.scala 129:34] + wire _T_56 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 131:26] + wire _T_57 = _T_55 | _T_56; // @[AXI4SlaveModule.scala 130:34] reg [30:0] r_2; // @[Reg.scala 27:20] wire [30:0] in_aw_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [30:0] _GEN_13 = _T_1 ? in_aw_bits_addr : r_2; // @[Reg.scala 28:19 Reg.scala 28:23 Reg.scala 27:20] @@ -107,12 +107,12 @@ module AXI4UART( wire [1:0] in_aw_bits_id = auto_in_aw_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [1:0] r_5; // @[Reg.scala 15:16] wire [1:0] in_ar_bits_id = auto_in_ar_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - reg [31:0] txfifo; // @[AXI4UART.scala 29:21] - reg [31:0] stat; // @[AXI4UART.scala 30:23] - reg [31:0] ctrl; // @[AXI4UART.scala 31:23] - wire _T_76 = _GEN_13[3:0] == 4'h4; // @[AXI4UART.scala 33:43] + reg [31:0] txfifo; // @[AXI4UART.scala 28:21] + reg [31:0] stat; // @[AXI4UART.scala 29:23] + reg [31:0] ctrl; // @[AXI4UART.scala 30:23] + wire _T_76 = _GEN_13[3:0] == 4'h4; // @[AXI4UART.scala 32:43] wire [63:0] in_w_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [7:0] _T_88 = in_w_bits_strb >> _GEN_13[2:0]; // @[AXI4UART.scala 45:74] + wire [7:0] _T_88 = in_w_bits_strb >> _GEN_13[2:0]; // @[AXI4UART.scala 44:74] wire [7:0] lo_lo_lo_1 = _T_88[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] lo_lo_hi_1 = _T_88[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] lo_hi_lo_1 = _T_88[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] @@ -139,31 +139,31 @@ module AXI4UART( wire [63:0] _GEN_22 = {{32'd0}, txfifo}; // @[BitUtils.scala 17:36] wire [63:0] _T_121 = _GEN_22 & _T_120; // @[BitUtils.scala 17:36] wire [63:0] _T_122 = _T_119 | _T_121; // @[BitUtils.scala 17:25] - wire [63:0] _GEN_18 = _T_2 & _T_76 ? _T_122 : {{32'd0}, txfifo}; // @[RegMap.scala 14:48 RegMap.scala 14:52 AXI4UART.scala 29:21] + wire [63:0] _GEN_18 = _T_2 & _T_76 ? _T_122 : {{32'd0}, txfifo}; // @[RegMap.scala 14:48 RegMap.scala 14:52 AXI4UART.scala 28:21] wire [63:0] _GEN_23 = {{32'd0}, stat}; // @[BitUtils.scala 17:36] wire [63:0] _T_127 = _GEN_23 & _T_120; // @[BitUtils.scala 17:36] wire [63:0] _T_128 = _T_119 | _T_127; // @[BitUtils.scala 17:25] - wire [63:0] _GEN_19 = _T_2 & _GEN_13[3:0] == 4'h8 ? _T_128 : {{32'd0}, stat}; // @[RegMap.scala 14:48 RegMap.scala 14:52 AXI4UART.scala 30:23] + wire [63:0] _GEN_19 = _T_2 & _GEN_13[3:0] == 4'h8 ? _T_128 : {{32'd0}, stat}; // @[RegMap.scala 14:48 RegMap.scala 14:52 AXI4UART.scala 29:23] wire [63:0] _GEN_24 = {{32'd0}, ctrl}; // @[BitUtils.scala 17:36] wire [63:0] _T_133 = _GEN_24 & _T_120; // @[BitUtils.scala 17:36] wire [63:0] _T_134 = _T_119 | _T_133; // @[BitUtils.scala 17:25] - wire [63:0] _GEN_20 = _T_2 & _GEN_13[3:0] == 4'hc ? _T_134 : {{32'd0}, ctrl}; // @[RegMap.scala 14:48 RegMap.scala 14:52 AXI4UART.scala 31:23] + wire [63:0] _GEN_20 = _T_2 & _GEN_13[3:0] == 4'hc ? _T_134 : {{32'd0}, ctrl}; // @[RegMap.scala 14:48 RegMap.scala 14:52 AXI4UART.scala 30:23] wire [7:0] in_aw_bits_len = auto_in_aw_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [2:0] in_aw_bits_size = auto_in_aw_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire in_aw_bits_lock = auto_in_aw_bits_lock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_aw_bits_cache = auto_in_aw_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [2:0] in_aw_bits_prot = auto_in_aw_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_aw_bits_qos = auto_in_aw_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 162:16] - wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 159:18] + wire [1:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 161:16] + wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 158:18] wire [2:0] in_ar_bits_size = auto_in_ar_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire in_ar_bits_lock = auto_in_ar_bits_lock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_ar_bits_cache = auto_in_ar_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [2:0] in_ar_bits_prot = auto_in_ar_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_ar_bits_qos = auto_in_ar_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 164:16] + wire [1:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 163:16] wire [63:0] in_r_bits_data = {{32'd0}, _T_116}; // @[Nodes.scala 1210:84 RegMap.scala 12:11] - wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 139:18] + wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 138:18] assign auto_in_aw_ready = in_aw_ready; // @[LazyModule.scala 309:16] assign auto_in_w_ready = in_w_ready; // @[LazyModule.scala 309:16] assign auto_in_b_valid = in_b_valid; // @[LazyModule.scala 309:16] @@ -175,21 +175,21 @@ module AXI4UART( assign auto_in_r_bits_data = in_r_bits_data; // @[LazyModule.scala 309:16] assign auto_in_r_bits_resp = in_b_bits_resp; // @[LazyModule.scala 309:16] assign auto_in_r_bits_last = in_r_bits_last; // @[LazyModule.scala 309:16] - assign io_extra_out_valid = _GEN_13[3:0] == 4'h4 & _T_2; // @[AXI4UART.scala 33:51] - assign io_extra_out_ch = in_w_bits_data[7:0]; // @[AXI4UART.scala 34:42] - assign io_extra_in_valid = _GEN_10[3:0] == 4'h0 & _T_4; // @[AXI4UART.scala 35:50] + assign io_extra_out_valid = _GEN_13[3:0] == 4'h4 & _T_2; // @[AXI4UART.scala 32:51] + assign io_extra_out_ch = in_w_bits_data[7:0]; // @[AXI4UART.scala 33:42] + assign io_extra_in_valid = _GEN_10[3:0] == 4'h0 & _T_4; // @[AXI4UART.scala 34:50] always @(posedge clock) begin - if (reset) begin // @[AXI4SlaveModule.scala 80:22] - state <= 2'h0; // @[AXI4SlaveModule.scala 80:22] + if (reset) begin // @[AXI4SlaveModule.scala 79:22] + state <= 2'h0; // @[AXI4SlaveModule.scala 79:22] end else if (_T_15) begin // @[Conditional.scala 40:58] - if (_T_1) begin // @[AXI4SlaveModule.scala 87:25] - state <= 2'h2; // @[AXI4SlaveModule.scala 88:15] - end else if (_T) begin // @[AXI4SlaveModule.scala 84:25] - state <= 2'h1; // @[AXI4SlaveModule.scala 85:15] + if (_T_1) begin // @[AXI4SlaveModule.scala 86:25] + state <= 2'h2; // @[AXI4SlaveModule.scala 87:15] + end else if (_T) begin // @[AXI4SlaveModule.scala 83:25] + state <= 2'h1; // @[AXI4SlaveModule.scala 84:15] end end else if (_T_18) begin // @[Conditional.scala 39:67] - if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 92:42] - state <= 2'h0; // @[AXI4SlaveModule.scala 93:15] + if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 91:42] + state <= 2'h0; // @[AXI4SlaveModule.scala 92:15] end end else if (_T_21) begin // @[Conditional.scala 39:67] state <= _GEN_3; @@ -198,9 +198,9 @@ module AXI4UART( end if (reset) begin // @[Counter.scala 60:40] value <= 8'h0; // @[Counter.scala 60:40] - end else if (_T_4) begin // @[AXI4SlaveModule.scala 120:23] - if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 122:28] - value <= 8'h0; // @[AXI4SlaveModule.scala 123:17] + end else if (_T_4) begin // @[AXI4SlaveModule.scala 119:23] + if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 121:28] + value <= 8'h0; // @[AXI4SlaveModule.scala 122:17] end else begin value <= _value_T_1; // @[Counter.scala 76:15] end @@ -227,13 +227,13 @@ module AXI4UART( r_5 <= in_ar_bits_id; // @[Reg.scala 16:23] end txfifo <= _GEN_18[31:0]; - if (reset) begin // @[AXI4UART.scala 30:23] - stat <= 32'h1; // @[AXI4UART.scala 30:23] + if (reset) begin // @[AXI4UART.scala 29:23] + stat <= 32'h1; // @[AXI4UART.scala 29:23] end else begin stat <= _GEN_19[31:0]; end - if (reset) begin // @[AXI4UART.scala 31:23] - ctrl <= 32'h0; // @[AXI4UART.scala 31:23] + if (reset) begin // @[AXI4UART.scala 30:23] + ctrl <= 32'h0; // @[AXI4UART.scala 30:23] end else begin ctrl <= _GEN_20[31:0]; end @@ -243,70 +243,37 @@ module AXI4UART( `endif if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin $fwrite(32'h80000002, - "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:72 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" - ); // @[AXI4SlaveModule.scala 72:11] + "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:71 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" + ); // @[AXI4SlaveModule.scala 71:11] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 72:11] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin $fwrite(32'h80000002, - "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:75 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" - ); // @[AXI4SlaveModule.scala 75:11] + "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:74 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" + ); // @[AXI4SlaveModule.scala 74:11] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 75:11] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T & ~(_T_57 | reset)) begin - $fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:127 assert(\n"); // @[AXI4SlaveModule.scala 127:13] + $fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:126 assert(\n"); // @[AXI4SlaveModule.scala 126:13] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS - `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T & ~(_T_57 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 127:13] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS end // Register and memory initialization `ifdef RANDOMIZE_GARBAGE_ASSIGN @@ -372,3 +339,4 @@ end // initial `endif `endif // SYNTHESIS endmodule + diff --git a/vcs/testbench/SimMMIO/AXI4VGA.v b/vcs/testbench/SimMMIO/AXI4VGA.v index 3fa28f2..cf2a737 100644 --- a/vcs/testbench/SimMMIO/AXI4VGA.v +++ b/vcs/testbench/SimMMIO/AXI4VGA.v @@ -178,7 +178,7 @@ module AXI4VGA( wire [16:0] hi = vCounterIsOdd ? fbPixelAddrV1 : fbPixelAddrV0; // @[AXI4VGA.scala 166:35] wire [18:0] _T_17 = {hi,2'h0}; // @[Cat.scala 30:58] reg REG_1; // @[AXI4VGA.scala 167:31] - AXI4RAM_1 fb ( // @[AXI4VGA.scala 115:30] + AXI4RAM fb ( // @[AXI4VGA.scala 115:30] .clock(fb_clock), .reset(fb_reset), .auto_in_aw_ready(fb_auto_in_aw_ready), @@ -425,3 +425,4 @@ end // initial `endif `endif // SYNTHESIS endmodule + diff --git a/vcs/testbench/SimMMIO/AXI4Xbar_1.v b/vcs/testbench/SimMMIO/AXI4Xbar.v similarity index 58% rename from vcs/testbench/SimMMIO/AXI4Xbar_1.v rename to vcs/testbench/SimMMIO/AXI4Xbar.v index 7d23da3..d27b796 100644 --- a/vcs/testbench/SimMMIO/AXI4Xbar_1.v +++ b/vcs/testbench/SimMMIO/AXI4Xbar.v @@ -1,4 +1,4 @@ -module AXI4Xbar_1( +module AXI4Xbar( input clock, input reset, output auto_in_aw_ready, @@ -38,6 +38,43 @@ module AXI4Xbar_1( output [63:0] auto_in_r_bits_data, output [1:0] auto_in_r_bits_resp, output auto_in_r_bits_last, + input auto_out_5_aw_ready, + output auto_out_5_aw_valid, + output [1:0] auto_out_5_aw_bits_id, + output [30:0] auto_out_5_aw_bits_addr, + output [7:0] auto_out_5_aw_bits_len, + output [2:0] auto_out_5_aw_bits_size, + output [1:0] auto_out_5_aw_bits_burst, + output auto_out_5_aw_bits_lock, + output [3:0] auto_out_5_aw_bits_cache, + output [2:0] auto_out_5_aw_bits_prot, + output [3:0] auto_out_5_aw_bits_qos, + input auto_out_5_w_ready, + output auto_out_5_w_valid, + output [63:0] auto_out_5_w_bits_data, + output [7:0] auto_out_5_w_bits_strb, + output auto_out_5_w_bits_last, + output auto_out_5_b_ready, + input auto_out_5_b_valid, + input [1:0] auto_out_5_b_bits_id, + input [1:0] auto_out_5_b_bits_resp, + input auto_out_5_ar_ready, + output auto_out_5_ar_valid, + output [1:0] auto_out_5_ar_bits_id, + output [30:0] auto_out_5_ar_bits_addr, + output [7:0] auto_out_5_ar_bits_len, + output [2:0] auto_out_5_ar_bits_size, + output [1:0] auto_out_5_ar_bits_burst, + output auto_out_5_ar_bits_lock, + output [3:0] auto_out_5_ar_bits_cache, + output [2:0] auto_out_5_ar_bits_prot, + output [3:0] auto_out_5_ar_bits_qos, + output auto_out_5_r_ready, + input auto_out_5_r_valid, + input [1:0] auto_out_5_r_bits_id, + input [63:0] auto_out_5_r_bits_data, + input [1:0] auto_out_5_r_bits_resp, + input auto_out_5_r_bits_last, input auto_out_4_aw_ready, output auto_out_4_aw_valid, output [1:0] auto_out_4_aw_bits_id, @@ -243,18 +280,20 @@ module AXI4Xbar_1( reg [31:0] _RAND_20; reg [31:0] _RAND_21; reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; `endif // RANDOMIZE_REG_INIT wire awIn_0_clock; // @[Xbar.scala 62:47] wire awIn_0_reset; // @[Xbar.scala 62:47] wire awIn_0_io_enq_ready; // @[Xbar.scala 62:47] wire awIn_0_io_enq_valid; // @[Xbar.scala 62:47] - wire [4:0] awIn_0_io_enq_bits; // @[Xbar.scala 62:47] + wire [5:0] awIn_0_io_enq_bits; // @[Xbar.scala 62:47] wire awIn_0_io_deq_ready; // @[Xbar.scala 62:47] wire awIn_0_io_deq_valid; // @[Xbar.scala 62:47] - wire [4:0] awIn_0_io_deq_bits; // @[Xbar.scala 62:47] + wire [5:0] awIn_0_io_deq_bits; // @[Xbar.scala 62:47] wire [30:0] _T = auto_in_ar_bits_addr ^ 31'h40200000; // @[Parameters.scala 137:31] wire [31:0] _T_1 = {1'b0,$signed(_T)}; // @[Parameters.scala 137:49] - wire [31:0] _T_3 = $signed(_T_1) & 32'sh50202000; // @[Parameters.scala 137:52] + wire [31:0] _T_3 = $signed(_T_1) & 32'sh50242000; // @[Parameters.scala 137:52] wire requestARIO_0_0 = $signed(_T_3) == 32'sh0; // @[Parameters.scala 137:67] wire [30:0] _T_5 = auto_in_ar_bits_addr ^ 31'h50000000; // @[Parameters.scala 137:31] wire [31:0] _T_6 = {1'b0,$signed(_T_5)}; // @[Parameters.scala 137:49] @@ -262,7 +301,7 @@ module AXI4Xbar_1( wire requestARIO_0_1 = $signed(_T_8) == 32'sh0; // @[Parameters.scala 137:67] wire [30:0] _T_10 = auto_in_ar_bits_addr ^ 31'h40000000; // @[Parameters.scala 137:31] wire [31:0] _T_11 = {1'b0,$signed(_T_10)}; // @[Parameters.scala 137:49] - wire [31:0] _T_13 = $signed(_T_11) & 32'sh50202000; // @[Parameters.scala 137:52] + wire [31:0] _T_13 = $signed(_T_11) & 32'sh50242000; // @[Parameters.scala 137:52] wire requestARIO_0_2 = $signed(_T_13) == 32'sh0; // @[Parameters.scala 137:67] wire [30:0] _T_15 = auto_in_ar_bits_addr ^ 31'h10000000; // @[Parameters.scala 137:31] wire [31:0] _T_16 = {1'b0,$signed(_T_15)}; // @[Parameters.scala 137:49] @@ -270,268 +309,309 @@ module AXI4Xbar_1( wire requestARIO_0_3 = $signed(_T_18) == 32'sh0; // @[Parameters.scala 137:67] wire [30:0] _T_20 = auto_in_ar_bits_addr ^ 31'h40002000; // @[Parameters.scala 137:31] wire [31:0] _T_21 = {1'b0,$signed(_T_20)}; // @[Parameters.scala 137:49] - wire [31:0] _T_23 = $signed(_T_21) & 32'sh50202000; // @[Parameters.scala 137:52] + wire [31:0] _T_23 = $signed(_T_21) & 32'sh50242000; // @[Parameters.scala 137:52] wire requestARIO_0_4 = $signed(_T_23) == 32'sh0; // @[Parameters.scala 137:67] - wire [30:0] _T_25 = auto_in_aw_bits_addr ^ 31'h40200000; // @[Parameters.scala 137:31] + wire [30:0] _T_25 = auto_in_ar_bits_addr ^ 31'h40040000; // @[Parameters.scala 137:31] wire [31:0] _T_26 = {1'b0,$signed(_T_25)}; // @[Parameters.scala 137:49] - wire [31:0] _T_28 = $signed(_T_26) & 32'sh50202000; // @[Parameters.scala 137:52] - wire requestAWIO_0_0 = $signed(_T_28) == 32'sh0; // @[Parameters.scala 137:67] - wire [30:0] _T_30 = auto_in_aw_bits_addr ^ 31'h50000000; // @[Parameters.scala 137:31] + wire [31:0] _T_28 = $signed(_T_26) & 32'sh50240000; // @[Parameters.scala 137:52] + wire requestARIO_0_5 = $signed(_T_28) == 32'sh0; // @[Parameters.scala 137:67] + wire [30:0] _T_30 = auto_in_aw_bits_addr ^ 31'h40200000; // @[Parameters.scala 137:31] wire [31:0] _T_31 = {1'b0,$signed(_T_30)}; // @[Parameters.scala 137:49] - wire [31:0] _T_33 = $signed(_T_31) & 32'sh50000000; // @[Parameters.scala 137:52] - wire requestAWIO_0_1 = $signed(_T_33) == 32'sh0; // @[Parameters.scala 137:67] - wire [30:0] _T_35 = auto_in_aw_bits_addr ^ 31'h40000000; // @[Parameters.scala 137:31] + wire [31:0] _T_33 = $signed(_T_31) & 32'sh50242000; // @[Parameters.scala 137:52] + wire requestAWIO_0_0 = $signed(_T_33) == 32'sh0; // @[Parameters.scala 137:67] + wire [30:0] _T_35 = auto_in_aw_bits_addr ^ 31'h50000000; // @[Parameters.scala 137:31] wire [31:0] _T_36 = {1'b0,$signed(_T_35)}; // @[Parameters.scala 137:49] - wire [31:0] _T_38 = $signed(_T_36) & 32'sh50202000; // @[Parameters.scala 137:52] - wire requestAWIO_0_2 = $signed(_T_38) == 32'sh0; // @[Parameters.scala 137:67] - wire [30:0] _T_40 = auto_in_aw_bits_addr ^ 31'h10000000; // @[Parameters.scala 137:31] + wire [31:0] _T_38 = $signed(_T_36) & 32'sh50000000; // @[Parameters.scala 137:52] + wire requestAWIO_0_1 = $signed(_T_38) == 32'sh0; // @[Parameters.scala 137:67] + wire [30:0] _T_40 = auto_in_aw_bits_addr ^ 31'h40000000; // @[Parameters.scala 137:31] wire [31:0] _T_41 = {1'b0,$signed(_T_40)}; // @[Parameters.scala 137:49] - wire [31:0] _T_43 = $signed(_T_41) & 32'sh50000000; // @[Parameters.scala 137:52] - wire requestAWIO_0_3 = $signed(_T_43) == 32'sh0; // @[Parameters.scala 137:67] - wire [30:0] _T_45 = auto_in_aw_bits_addr ^ 31'h40002000; // @[Parameters.scala 137:31] + wire [31:0] _T_43 = $signed(_T_41) & 32'sh50242000; // @[Parameters.scala 137:52] + wire requestAWIO_0_2 = $signed(_T_43) == 32'sh0; // @[Parameters.scala 137:67] + wire [30:0] _T_45 = auto_in_aw_bits_addr ^ 31'h10000000; // @[Parameters.scala 137:31] wire [31:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49] - wire [31:0] _T_48 = $signed(_T_46) & 32'sh50202000; // @[Parameters.scala 137:52] - wire requestAWIO_0_4 = $signed(_T_48) == 32'sh0; // @[Parameters.scala 137:67] - wire [1:0] lo = {requestAWIO_0_1,requestAWIO_0_0}; // @[Xbar.scala 71:75] - wire [2:0] hi = {requestAWIO_0_4,requestAWIO_0_3,requestAWIO_0_2}; // @[Xbar.scala 71:75] + wire [31:0] _T_48 = $signed(_T_46) & 32'sh50000000; // @[Parameters.scala 137:52] + wire requestAWIO_0_3 = $signed(_T_48) == 32'sh0; // @[Parameters.scala 137:67] + wire [30:0] _T_50 = auto_in_aw_bits_addr ^ 31'h40002000; // @[Parameters.scala 137:31] + wire [31:0] _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 137:49] + wire [31:0] _T_53 = $signed(_T_51) & 32'sh50242000; // @[Parameters.scala 137:52] + wire requestAWIO_0_4 = $signed(_T_53) == 32'sh0; // @[Parameters.scala 137:67] + wire [30:0] _T_55 = auto_in_aw_bits_addr ^ 31'h40040000; // @[Parameters.scala 137:31] + wire [31:0] _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 137:49] + wire [31:0] _T_58 = $signed(_T_56) & 32'sh50240000; // @[Parameters.scala 137:52] + wire requestAWIO_0_5 = $signed(_T_58) == 32'sh0; // @[Parameters.scala 137:67] + wire [2:0] lo = {requestAWIO_0_2,requestAWIO_0_1,requestAWIO_0_0}; // @[Xbar.scala 71:75] + wire [2:0] hi = {requestAWIO_0_5,requestAWIO_0_4,requestAWIO_0_3}; // @[Xbar.scala 71:75] wire requestWIO_0_0 = awIn_0_io_deq_bits[0]; // @[Xbar.scala 72:73] wire requestWIO_0_1 = awIn_0_io_deq_bits[1]; // @[Xbar.scala 72:73] wire requestWIO_0_2 = awIn_0_io_deq_bits[2]; // @[Xbar.scala 72:73] wire requestWIO_0_3 = awIn_0_io_deq_bits[3]; // @[Xbar.scala 72:73] wire requestWIO_0_4 = awIn_0_io_deq_bits[4]; // @[Xbar.scala 72:73] - reg REG_37; // @[Xbar.scala 249:23] - wire [4:0] lo_12 = {auto_out_4_r_valid,auto_out_3_r_valid,auto_out_2_r_valid,auto_out_1_r_valid,auto_out_0_r_valid}; // @[Cat.scala 30:58] - reg [4:0] REG_38; // @[Arbiter.scala 23:23] - wire [4:0] _T_608 = ~REG_38; // @[Arbiter.scala 24:30] - wire [4:0] hi_12 = lo_12 & _T_608; // @[Arbiter.scala 24:28] - wire [9:0] _T_609 = {hi_12,auto_out_4_r_valid,auto_out_3_r_valid,auto_out_2_r_valid,auto_out_1_r_valid, + wire requestWIO_0_5 = awIn_0_io_deq_bits[5]; // @[Xbar.scala 72:73] + reg REG_41; // @[Xbar.scala 249:23] + wire [5:0] lo_12 = {auto_out_5_r_valid,auto_out_4_r_valid,auto_out_3_r_valid,auto_out_2_r_valid,auto_out_1_r_valid, auto_out_0_r_valid}; // @[Cat.scala 30:58] - wire [9:0] _GEN_44 = {{1'd0}, _T_609[9:1]}; // @[package.scala 253:43] - wire [9:0] _T_611 = _T_609 | _GEN_44; // @[package.scala 253:43] - wire [9:0] _GEN_45 = {{2'd0}, _T_611[9:2]}; // @[package.scala 253:43] - wire [9:0] _T_613 = _T_611 | _GEN_45; // @[package.scala 253:43] - wire [9:0] _GEN_46 = {{4'd0}, _T_613[9:4]}; // @[package.scala 253:43] - wire [9:0] _T_615 = _T_613 | _GEN_46; // @[package.scala 253:43] - wire [9:0] _T_618 = {REG_38, 5'h0}; // @[Arbiter.scala 25:66] - wire [9:0] _GEN_47 = {{1'd0}, _T_615[9:1]}; // @[Arbiter.scala 25:58] - wire [9:0] _T_619 = _GEN_47 | _T_618; // @[Arbiter.scala 25:58] - wire [4:0] _T_622 = _T_619[9:5] & _T_619[4:0]; // @[Arbiter.scala 26:39] - wire [4:0] _T_623 = ~_T_622; // @[Arbiter.scala 26:18] - wire _T_643 = _T_623[0] & auto_out_0_r_valid; // @[Xbar.scala 257:63] - reg REG_39_0; // @[Xbar.scala 268:24] - wire _T_684_0 = REG_37 ? _T_643 : REG_39_0; // @[Xbar.scala 269:23] - wire [1:0] _T_729 = _T_684_0 ? auto_out_0_r_bits_id : 2'h0; // @[Mux.scala 27:72] - wire _T_644 = _T_623[1] & auto_out_1_r_valid; // @[Xbar.scala 257:63] - reg REG_39_1; // @[Xbar.scala 268:24] - wire _T_684_1 = REG_37 ? _T_644 : REG_39_1; // @[Xbar.scala 269:23] - wire [1:0] _T_730 = _T_684_1 ? auto_out_1_r_bits_id : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_734 = _T_729 | _T_730; // @[Mux.scala 27:72] - wire _T_645 = _T_623[2] & auto_out_2_r_valid; // @[Xbar.scala 257:63] - reg REG_39_2; // @[Xbar.scala 268:24] - wire _T_684_2 = REG_37 ? _T_645 : REG_39_2; // @[Xbar.scala 269:23] - wire [1:0] _T_731 = _T_684_2 ? auto_out_2_r_bits_id : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_735 = _T_734 | _T_731; // @[Mux.scala 27:72] - wire _T_646 = _T_623[3] & auto_out_3_r_valid; // @[Xbar.scala 257:63] - reg REG_39_3; // @[Xbar.scala 268:24] - wire _T_684_3 = REG_37 ? _T_646 : REG_39_3; // @[Xbar.scala 269:23] - wire [1:0] _T_732 = _T_684_3 ? auto_out_3_r_bits_id : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_736 = _T_735 | _T_732; // @[Mux.scala 27:72] - wire _T_647 = _T_623[4] & auto_out_4_r_valid; // @[Xbar.scala 257:63] - reg REG_39_4; // @[Xbar.scala 268:24] - wire _T_684_4 = REG_37 ? _T_647 : REG_39_4; // @[Xbar.scala 269:23] - wire [1:0] _T_733 = _T_684_4 ? auto_out_4_r_bits_id : 2'h0; // @[Mux.scala 27:72] - wire [1:0] in_0_r_bits_id = _T_736 | _T_733; // @[Mux.scala 27:72] - reg REG_40; // @[Xbar.scala 249:23] - wire [4:0] lo_14 = {auto_out_4_b_valid,auto_out_3_b_valid,auto_out_2_b_valid,auto_out_1_b_valid,auto_out_0_b_valid}; // @[Cat.scala 30:58] - reg [4:0] REG_41; // @[Arbiter.scala 23:23] - wire [4:0] _T_747 = ~REG_41; // @[Arbiter.scala 24:30] - wire [4:0] hi_14 = lo_14 & _T_747; // @[Arbiter.scala 24:28] - wire [9:0] _T_748 = {hi_14,auto_out_4_b_valid,auto_out_3_b_valid,auto_out_2_b_valid,auto_out_1_b_valid, + reg [5:0] REG_42; // @[Arbiter.scala 23:23] + wire [5:0] _T_678 = ~REG_42; // @[Arbiter.scala 24:30] + wire [5:0] hi_12 = lo_12 & _T_678; // @[Arbiter.scala 24:28] + wire [11:0] _T_679 = {hi_12,auto_out_5_r_valid,auto_out_4_r_valid,auto_out_3_r_valid,auto_out_2_r_valid, + auto_out_1_r_valid,auto_out_0_r_valid}; // @[Cat.scala 30:58] + wire [11:0] _GEN_48 = {{1'd0}, _T_679[11:1]}; // @[package.scala 253:43] + wire [11:0] _T_681 = _T_679 | _GEN_48; // @[package.scala 253:43] + wire [11:0] _GEN_49 = {{2'd0}, _T_681[11:2]}; // @[package.scala 253:43] + wire [11:0] _T_683 = _T_681 | _GEN_49; // @[package.scala 253:43] + wire [11:0] _GEN_50 = {{4'd0}, _T_683[11:4]}; // @[package.scala 253:43] + wire [11:0] _T_685 = _T_683 | _GEN_50; // @[package.scala 253:43] + wire [11:0] _T_688 = {REG_42, 6'h0}; // @[Arbiter.scala 25:66] + wire [11:0] _GEN_51 = {{1'd0}, _T_685[11:1]}; // @[Arbiter.scala 25:58] + wire [11:0] _T_689 = _GEN_51 | _T_688; // @[Arbiter.scala 25:58] + wire [5:0] _T_692 = _T_689[11:6] & _T_689[5:0]; // @[Arbiter.scala 26:39] + wire [5:0] _T_693 = ~_T_692; // @[Arbiter.scala 26:18] + wire _T_714 = _T_693[0] & auto_out_0_r_valid; // @[Xbar.scala 257:63] + reg REG_43_0; // @[Xbar.scala 268:24] + wire _T_762_0 = REG_41 ? _T_714 : REG_43_0; // @[Xbar.scala 269:23] + wire [1:0] _T_816 = _T_762_0 ? auto_out_0_r_bits_id : 2'h0; // @[Mux.scala 27:72] + wire _T_715 = _T_693[1] & auto_out_1_r_valid; // @[Xbar.scala 257:63] + reg REG_43_1; // @[Xbar.scala 268:24] + wire _T_762_1 = REG_41 ? _T_715 : REG_43_1; // @[Xbar.scala 269:23] + wire [1:0] _T_817 = _T_762_1 ? auto_out_1_r_bits_id : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_822 = _T_816 | _T_817; // @[Mux.scala 27:72] + wire _T_716 = _T_693[2] & auto_out_2_r_valid; // @[Xbar.scala 257:63] + reg REG_43_2; // @[Xbar.scala 268:24] + wire _T_762_2 = REG_41 ? _T_716 : REG_43_2; // @[Xbar.scala 269:23] + wire [1:0] _T_818 = _T_762_2 ? auto_out_2_r_bits_id : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_823 = _T_822 | _T_818; // @[Mux.scala 27:72] + wire _T_717 = _T_693[3] & auto_out_3_r_valid; // @[Xbar.scala 257:63] + reg REG_43_3; // @[Xbar.scala 268:24] + wire _T_762_3 = REG_41 ? _T_717 : REG_43_3; // @[Xbar.scala 269:23] + wire [1:0] _T_819 = _T_762_3 ? auto_out_3_r_bits_id : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_824 = _T_823 | _T_819; // @[Mux.scala 27:72] + wire _T_718 = _T_693[4] & auto_out_4_r_valid; // @[Xbar.scala 257:63] + reg REG_43_4; // @[Xbar.scala 268:24] + wire _T_762_4 = REG_41 ? _T_718 : REG_43_4; // @[Xbar.scala 269:23] + wire [1:0] _T_820 = _T_762_4 ? auto_out_4_r_bits_id : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_825 = _T_824 | _T_820; // @[Mux.scala 27:72] + wire _T_719 = _T_693[5] & auto_out_5_r_valid; // @[Xbar.scala 257:63] + reg REG_43_5; // @[Xbar.scala 268:24] + wire _T_762_5 = REG_41 ? _T_719 : REG_43_5; // @[Xbar.scala 269:23] + wire [1:0] _T_821 = _T_762_5 ? auto_out_5_r_bits_id : 2'h0; // @[Mux.scala 27:72] + wire [1:0] in_0_r_bits_id = _T_825 | _T_821; // @[Mux.scala 27:72] + reg REG_44; // @[Xbar.scala 249:23] + wire [5:0] lo_14 = {auto_out_5_b_valid,auto_out_4_b_valid,auto_out_3_b_valid,auto_out_2_b_valid,auto_out_1_b_valid, auto_out_0_b_valid}; // @[Cat.scala 30:58] - wire [9:0] _GEN_48 = {{1'd0}, _T_748[9:1]}; // @[package.scala 253:43] - wire [9:0] _T_750 = _T_748 | _GEN_48; // @[package.scala 253:43] - wire [9:0] _GEN_49 = {{2'd0}, _T_750[9:2]}; // @[package.scala 253:43] - wire [9:0] _T_752 = _T_750 | _GEN_49; // @[package.scala 253:43] - wire [9:0] _GEN_50 = {{4'd0}, _T_752[9:4]}; // @[package.scala 253:43] - wire [9:0] _T_754 = _T_752 | _GEN_50; // @[package.scala 253:43] - wire [9:0] _T_757 = {REG_41, 5'h0}; // @[Arbiter.scala 25:66] - wire [9:0] _GEN_51 = {{1'd0}, _T_754[9:1]}; // @[Arbiter.scala 25:58] - wire [9:0] _T_758 = _GEN_51 | _T_757; // @[Arbiter.scala 25:58] - wire [4:0] _T_761 = _T_758[9:5] & _T_758[4:0]; // @[Arbiter.scala 26:39] - wire [4:0] _T_762 = ~_T_761; // @[Arbiter.scala 26:18] - wire _T_782 = _T_762[0] & auto_out_0_b_valid; // @[Xbar.scala 257:63] - reg REG_42_0; // @[Xbar.scala 268:24] - wire _T_823_0 = REG_40 ? _T_782 : REG_42_0; // @[Xbar.scala 269:23] - wire [1:0] _T_850 = _T_823_0 ? auto_out_0_b_bits_id : 2'h0; // @[Mux.scala 27:72] - wire _T_783 = _T_762[1] & auto_out_1_b_valid; // @[Xbar.scala 257:63] - reg REG_42_1; // @[Xbar.scala 268:24] - wire _T_823_1 = REG_40 ? _T_783 : REG_42_1; // @[Xbar.scala 269:23] - wire [1:0] _T_851 = _T_823_1 ? auto_out_1_b_bits_id : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_855 = _T_850 | _T_851; // @[Mux.scala 27:72] - wire _T_784 = _T_762[2] & auto_out_2_b_valid; // @[Xbar.scala 257:63] - reg REG_42_2; // @[Xbar.scala 268:24] - wire _T_823_2 = REG_40 ? _T_784 : REG_42_2; // @[Xbar.scala 269:23] - wire [1:0] _T_852 = _T_823_2 ? auto_out_2_b_bits_id : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_856 = _T_855 | _T_852; // @[Mux.scala 27:72] - wire _T_785 = _T_762[3] & auto_out_3_b_valid; // @[Xbar.scala 257:63] - reg REG_42_3; // @[Xbar.scala 268:24] - wire _T_823_3 = REG_40 ? _T_785 : REG_42_3; // @[Xbar.scala 269:23] - wire [1:0] _T_853 = _T_823_3 ? auto_out_3_b_bits_id : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_857 = _T_856 | _T_853; // @[Mux.scala 27:72] - wire _T_786 = _T_762[4] & auto_out_4_b_valid; // @[Xbar.scala 257:63] - reg REG_42_4; // @[Xbar.scala 268:24] - wire _T_823_4 = REG_40 ? _T_786 : REG_42_4; // @[Xbar.scala 269:23] - wire [1:0] _T_854 = _T_823_4 ? auto_out_4_b_bits_id : 2'h0; // @[Mux.scala 27:72] - wire [1:0] in_0_b_bits_id = _T_857 | _T_854; // @[Mux.scala 27:72] - wire [3:0] _T_125 = 4'h1 << auto_in_ar_bits_id; // @[OneHot.scala 65:12] - wire [3:0] _T_127 = 4'h1 << auto_in_aw_bits_id; // @[OneHot.scala 65:12] - wire [3:0] _T_129 = 4'h1 << in_0_r_bits_id; // @[OneHot.scala 65:12] - wire [3:0] _T_131 = 4'h1 << in_0_b_bits_id; // @[OneHot.scala 65:12] + reg [5:0] REG_45; // @[Arbiter.scala 23:23] + wire [5:0] _T_837 = ~REG_45; // @[Arbiter.scala 24:30] + wire [5:0] hi_14 = lo_14 & _T_837; // @[Arbiter.scala 24:28] + wire [11:0] _T_838 = {hi_14,auto_out_5_b_valid,auto_out_4_b_valid,auto_out_3_b_valid,auto_out_2_b_valid, + auto_out_1_b_valid,auto_out_0_b_valid}; // @[Cat.scala 30:58] + wire [11:0] _GEN_52 = {{1'd0}, _T_838[11:1]}; // @[package.scala 253:43] + wire [11:0] _T_840 = _T_838 | _GEN_52; // @[package.scala 253:43] + wire [11:0] _GEN_53 = {{2'd0}, _T_840[11:2]}; // @[package.scala 253:43] + wire [11:0] _T_842 = _T_840 | _GEN_53; // @[package.scala 253:43] + wire [11:0] _GEN_54 = {{4'd0}, _T_842[11:4]}; // @[package.scala 253:43] + wire [11:0] _T_844 = _T_842 | _GEN_54; // @[package.scala 253:43] + wire [11:0] _T_847 = {REG_45, 6'h0}; // @[Arbiter.scala 25:66] + wire [11:0] _GEN_55 = {{1'd0}, _T_844[11:1]}; // @[Arbiter.scala 25:58] + wire [11:0] _T_848 = _GEN_55 | _T_847; // @[Arbiter.scala 25:58] + wire [5:0] _T_851 = _T_848[11:6] & _T_848[5:0]; // @[Arbiter.scala 26:39] + wire [5:0] _T_852 = ~_T_851; // @[Arbiter.scala 26:18] + wire _T_873 = _T_852[0] & auto_out_0_b_valid; // @[Xbar.scala 257:63] + reg REG_46_0; // @[Xbar.scala 268:24] + wire _T_921_0 = REG_44 ? _T_873 : REG_46_0; // @[Xbar.scala 269:23] + wire [1:0] _T_953 = _T_921_0 ? auto_out_0_b_bits_id : 2'h0; // @[Mux.scala 27:72] + wire _T_874 = _T_852[1] & auto_out_1_b_valid; // @[Xbar.scala 257:63] + reg REG_46_1; // @[Xbar.scala 268:24] + wire _T_921_1 = REG_44 ? _T_874 : REG_46_1; // @[Xbar.scala 269:23] + wire [1:0] _T_954 = _T_921_1 ? auto_out_1_b_bits_id : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_959 = _T_953 | _T_954; // @[Mux.scala 27:72] + wire _T_875 = _T_852[2] & auto_out_2_b_valid; // @[Xbar.scala 257:63] + reg REG_46_2; // @[Xbar.scala 268:24] + wire _T_921_2 = REG_44 ? _T_875 : REG_46_2; // @[Xbar.scala 269:23] + wire [1:0] _T_955 = _T_921_2 ? auto_out_2_b_bits_id : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_960 = _T_959 | _T_955; // @[Mux.scala 27:72] + wire _T_876 = _T_852[3] & auto_out_3_b_valid; // @[Xbar.scala 257:63] + reg REG_46_3; // @[Xbar.scala 268:24] + wire _T_921_3 = REG_44 ? _T_876 : REG_46_3; // @[Xbar.scala 269:23] + wire [1:0] _T_956 = _T_921_3 ? auto_out_3_b_bits_id : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_961 = _T_960 | _T_956; // @[Mux.scala 27:72] + wire _T_877 = _T_852[4] & auto_out_4_b_valid; // @[Xbar.scala 257:63] + reg REG_46_4; // @[Xbar.scala 268:24] + wire _T_921_4 = REG_44 ? _T_877 : REG_46_4; // @[Xbar.scala 269:23] + wire [1:0] _T_957 = _T_921_4 ? auto_out_4_b_bits_id : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_962 = _T_961 | _T_957; // @[Mux.scala 27:72] + wire _T_878 = _T_852[5] & auto_out_5_b_valid; // @[Xbar.scala 257:63] + reg REG_46_5; // @[Xbar.scala 268:24] + wire _T_921_5 = REG_44 ? _T_878 : REG_46_5; // @[Xbar.scala 269:23] + wire [1:0] _T_958 = _T_921_5 ? auto_out_5_b_bits_id : 2'h0; // @[Mux.scala 27:72] + wire [1:0] in_0_b_bits_id = _T_962 | _T_958; // @[Mux.scala 27:72] + wire [3:0] _T_149 = 4'h1 << auto_in_ar_bits_id; // @[OneHot.scala 65:12] + wire [3:0] _T_151 = 4'h1 << auto_in_aw_bits_id; // @[OneHot.scala 65:12] + wire [3:0] _T_153 = 4'h1 << in_0_r_bits_id; // @[OneHot.scala 65:12] + wire [3:0] _T_155 = 4'h1 << in_0_b_bits_id; // @[OneHot.scala 65:12] wire in_0_ar_ready = requestARIO_0_0 & auto_out_0_ar_ready | requestARIO_0_1 | requestARIO_0_2 & auto_out_2_ar_ready - | requestARIO_0_3 & auto_out_3_ar_ready | requestARIO_0_4 & auto_out_4_ar_ready; // @[Mux.scala 27:72] + | requestARIO_0_3 & auto_out_3_ar_ready | requestARIO_0_4 & auto_out_4_ar_ready | requestARIO_0_5 & + auto_out_5_ar_ready; // @[Mux.scala 27:72] reg REG_12; // @[Xbar.scala 111:34] - wire _T_329 = ~REG_12; // @[Xbar.scala 119:22] + wire _T_353 = ~REG_12; // @[Xbar.scala 119:22] reg REG_8; // @[Xbar.scala 111:34] - wire _T_274 = ~REG_8; // @[Xbar.scala 119:22] + wire _T_298 = ~REG_8; // @[Xbar.scala 119:22] reg REG_4; // @[Xbar.scala 111:34] - wire _T_219 = ~REG_4; // @[Xbar.scala 119:22] + wire _T_243 = ~REG_4; // @[Xbar.scala 119:22] reg REG; // @[Xbar.scala 111:34] - wire _T_164 = ~REG; // @[Xbar.scala 119:22] - wire _T_142 = in_0_ar_ready & auto_in_ar_valid; // @[Decoupled.scala 40:37] - wire _T_143 = _T_125[0] & _T_142; // @[Xbar.scala 126:25] - wire _T_602 = auto_out_0_r_valid | auto_out_1_r_valid | auto_out_2_r_valid | auto_out_3_r_valid | auto_out_4_r_valid; // @[Xbar.scala 253:36] - wire _T_700 = REG_39_0 & auto_out_0_r_valid | REG_39_1 & auto_out_1_r_valid | REG_39_2 & auto_out_2_r_valid | - REG_39_3 & auto_out_3_r_valid | REG_39_4 & auto_out_4_r_valid; // @[Mux.scala 27:72] - wire in_0_r_valid = REG_37 ? _T_602 : _T_700; // @[Xbar.scala 285:22] - wire _T_145 = auto_in_r_ready & in_0_r_valid; // @[Decoupled.scala 40:37] - wire in_0_r_bits_last = _T_684_0 & auto_out_0_r_bits_last | _T_684_1 & auto_out_1_r_bits_last | _T_684_2 & - auto_out_2_r_bits_last | _T_684_3 & auto_out_3_r_bits_last | _T_684_4 & auto_out_4_r_bits_last; // @[Mux.scala 27:72] - wire _T_147 = _T_129[0] & _T_145 & in_0_r_bits_last; // @[Xbar.scala 127:45] - wire _T_149 = REG + _T_143; // @[Xbar.scala 113:30] + wire _T_188 = ~REG; // @[Xbar.scala 119:22] + wire _T_166 = in_0_ar_ready & auto_in_ar_valid; // @[Decoupled.scala 40:37] + wire _T_167 = _T_149[0] & _T_166; // @[Xbar.scala 126:25] + wire _T_672 = auto_out_0_r_valid | auto_out_1_r_valid | auto_out_2_r_valid | auto_out_3_r_valid | auto_out_4_r_valid + | auto_out_5_r_valid; // @[Xbar.scala 253:36] + wire _T_781 = REG_43_0 & auto_out_0_r_valid | REG_43_1 & auto_out_1_r_valid | REG_43_2 & auto_out_2_r_valid | + REG_43_3 & auto_out_3_r_valid | REG_43_4 & auto_out_4_r_valid | REG_43_5 & auto_out_5_r_valid; // @[Mux.scala 27:72] + wire in_0_r_valid = REG_41 ? _T_672 : _T_781; // @[Xbar.scala 285:22] + wire _T_169 = auto_in_r_ready & in_0_r_valid; // @[Decoupled.scala 40:37] + wire in_0_r_bits_last = _T_762_0 & auto_out_0_r_bits_last | _T_762_1 & auto_out_1_r_bits_last | _T_762_2 & + auto_out_2_r_bits_last | _T_762_3 & auto_out_3_r_bits_last | _T_762_4 & auto_out_4_r_bits_last | _T_762_5 & + auto_out_5_r_bits_last; // @[Mux.scala 27:72] + wire _T_171 = _T_153[0] & _T_169 & in_0_r_bits_last; // @[Xbar.scala 127:45] + wire _T_173 = REG + _T_167; // @[Xbar.scala 113:30] wire in_0_aw_ready = requestAWIO_0_0 & auto_out_0_aw_ready | requestAWIO_0_1 & auto_out_1_aw_ready | requestAWIO_0_2 - & auto_out_2_aw_ready | requestAWIO_0_3 & auto_out_3_aw_ready | requestAWIO_0_4 & auto_out_4_aw_ready; // @[Mux.scala 27:72] + & auto_out_2_aw_ready | requestAWIO_0_3 & auto_out_3_aw_ready | requestAWIO_0_4 & auto_out_4_aw_ready | + requestAWIO_0_5 & auto_out_5_aw_ready; // @[Mux.scala 27:72] reg REG_16; // @[Xbar.scala 144:30] - wire _T_366 = REG_16 | awIn_0_io_enq_ready; // @[Xbar.scala 146:57] + wire _T_390 = REG_16 | awIn_0_io_enq_ready; // @[Xbar.scala 146:57] wire io_in_0_aw_ready = in_0_aw_ready & (REG_16 | awIn_0_io_enq_ready); // @[Xbar.scala 146:45] reg REG_14; // @[Xbar.scala 111:34] - wire _T_356 = ~REG_14; // @[Xbar.scala 119:22] + wire _T_380 = ~REG_14; // @[Xbar.scala 119:22] reg REG_10; // @[Xbar.scala 111:34] - wire _T_301 = ~REG_10; // @[Xbar.scala 119:22] + wire _T_325 = ~REG_10; // @[Xbar.scala 119:22] reg REG_6; // @[Xbar.scala 111:34] - wire _T_246 = ~REG_6; // @[Xbar.scala 119:22] + wire _T_270 = ~REG_6; // @[Xbar.scala 119:22] reg REG_2; // @[Xbar.scala 111:34] - wire _T_191 = ~REG_2; // @[Xbar.scala 119:22] - wire _T_170 = io_in_0_aw_ready & auto_in_aw_valid; // @[Decoupled.scala 40:37] - wire _T_171 = _T_127[0] & _T_170; // @[Xbar.scala 130:25] - wire _T_741 = auto_out_0_b_valid | auto_out_1_b_valid | auto_out_2_b_valid | auto_out_3_b_valid | auto_out_4_b_valid; // @[Xbar.scala 253:36] - wire _T_839 = REG_42_0 & auto_out_0_b_valid | REG_42_1 & auto_out_1_b_valid | REG_42_2 & auto_out_2_b_valid | - REG_42_3 & auto_out_3_b_valid | REG_42_4 & auto_out_4_b_valid; // @[Mux.scala 27:72] - wire in_0_b_valid = REG_40 ? _T_741 : _T_839; // @[Xbar.scala 285:22] - wire _T_173 = auto_in_b_ready & in_0_b_valid; // @[Decoupled.scala 40:37] - wire _T_174 = _T_131[0] & _T_173; // @[Xbar.scala 131:24] - wire _T_176 = REG_2 + _T_171; // @[Xbar.scala 113:30] - wire _T_198 = _T_125[1] & _T_142; // @[Xbar.scala 126:25] - wire _T_202 = _T_129[1] & _T_145 & in_0_r_bits_last; // @[Xbar.scala 127:45] - wire _T_204 = REG_4 + _T_198; // @[Xbar.scala 113:30] - wire _T_226 = _T_127[1] & _T_170; // @[Xbar.scala 130:25] - wire _T_229 = _T_131[1] & _T_173; // @[Xbar.scala 131:24] - wire _T_231 = REG_6 + _T_226; // @[Xbar.scala 113:30] - wire _T_253 = _T_125[2] & _T_142; // @[Xbar.scala 126:25] - wire _T_257 = _T_129[2] & _T_145 & in_0_r_bits_last; // @[Xbar.scala 127:45] - wire _T_259 = REG_8 + _T_253; // @[Xbar.scala 113:30] - wire _T_281 = _T_127[2] & _T_170; // @[Xbar.scala 130:25] - wire _T_284 = _T_131[2] & _T_173; // @[Xbar.scala 131:24] - wire _T_286 = REG_10 + _T_281; // @[Xbar.scala 113:30] - wire _T_308 = _T_125[3] & _T_142; // @[Xbar.scala 126:25] - wire _T_312 = _T_129[3] & _T_145 & in_0_r_bits_last; // @[Xbar.scala 127:45] - wire _T_314 = REG_12 + _T_308; // @[Xbar.scala 113:30] - wire _T_336 = _T_127[3] & _T_170; // @[Xbar.scala 130:25] - wire _T_339 = _T_131[3] & _T_173; // @[Xbar.scala 131:24] - wire _T_341 = REG_14 + _T_336; // @[Xbar.scala 113:30] - wire in_0_aw_valid = auto_in_aw_valid & _T_366; // @[Xbar.scala 145:45] - wire _T_371 = awIn_0_io_enq_ready & awIn_0_io_enq_valid; // @[Decoupled.scala 40:37] - wire _GEN_16 = _T_371 | REG_16; // @[Xbar.scala 148:38 Xbar.scala 148:48 Xbar.scala 144:30] - wire _T_372 = in_0_aw_ready & in_0_aw_valid; // @[Decoupled.scala 40:37] + wire _T_215 = ~REG_2; // @[Xbar.scala 119:22] + wire _T_194 = io_in_0_aw_ready & auto_in_aw_valid; // @[Decoupled.scala 40:37] + wire _T_195 = _T_151[0] & _T_194; // @[Xbar.scala 130:25] + wire _T_831 = auto_out_0_b_valid | auto_out_1_b_valid | auto_out_2_b_valid | auto_out_3_b_valid | auto_out_4_b_valid + | auto_out_5_b_valid; // @[Xbar.scala 253:36] + wire _T_940 = REG_46_0 & auto_out_0_b_valid | REG_46_1 & auto_out_1_b_valid | REG_46_2 & auto_out_2_b_valid | + REG_46_3 & auto_out_3_b_valid | REG_46_4 & auto_out_4_b_valid | REG_46_5 & auto_out_5_b_valid; // @[Mux.scala 27:72] + wire in_0_b_valid = REG_44 ? _T_831 : _T_940; // @[Xbar.scala 285:22] + wire _T_197 = auto_in_b_ready & in_0_b_valid; // @[Decoupled.scala 40:37] + wire _T_198 = _T_155[0] & _T_197; // @[Xbar.scala 131:24] + wire _T_200 = REG_2 + _T_195; // @[Xbar.scala 113:30] + wire _T_222 = _T_149[1] & _T_166; // @[Xbar.scala 126:25] + wire _T_226 = _T_153[1] & _T_169 & in_0_r_bits_last; // @[Xbar.scala 127:45] + wire _T_228 = REG_4 + _T_222; // @[Xbar.scala 113:30] + wire _T_250 = _T_151[1] & _T_194; // @[Xbar.scala 130:25] + wire _T_253 = _T_155[1] & _T_197; // @[Xbar.scala 131:24] + wire _T_255 = REG_6 + _T_250; // @[Xbar.scala 113:30] + wire _T_277 = _T_149[2] & _T_166; // @[Xbar.scala 126:25] + wire _T_281 = _T_153[2] & _T_169 & in_0_r_bits_last; // @[Xbar.scala 127:45] + wire _T_283 = REG_8 + _T_277; // @[Xbar.scala 113:30] + wire _T_305 = _T_151[2] & _T_194; // @[Xbar.scala 130:25] + wire _T_308 = _T_155[2] & _T_197; // @[Xbar.scala 131:24] + wire _T_310 = REG_10 + _T_305; // @[Xbar.scala 113:30] + wire _T_332 = _T_149[3] & _T_166; // @[Xbar.scala 126:25] + wire _T_336 = _T_153[3] & _T_169 & in_0_r_bits_last; // @[Xbar.scala 127:45] + wire _T_338 = REG_12 + _T_332; // @[Xbar.scala 113:30] + wire _T_360 = _T_151[3] & _T_194; // @[Xbar.scala 130:25] + wire _T_363 = _T_155[3] & _T_197; // @[Xbar.scala 131:24] + wire _T_365 = REG_14 + _T_360; // @[Xbar.scala 113:30] + wire in_0_aw_valid = auto_in_aw_valid & _T_390; // @[Xbar.scala 145:45] + wire _T_395 = awIn_0_io_enq_ready & awIn_0_io_enq_valid; // @[Decoupled.scala 40:37] + wire _GEN_16 = _T_395 | REG_16; // @[Xbar.scala 148:38 Xbar.scala 148:48 Xbar.scala 144:30] + wire _T_396 = in_0_aw_ready & in_0_aw_valid; // @[Decoupled.scala 40:37] wire in_0_w_valid = auto_in_w_valid & awIn_0_io_deq_valid; // @[Xbar.scala 152:43] wire in_0_w_ready = requestWIO_0_0 & auto_out_0_w_ready | requestWIO_0_1 & auto_out_1_w_ready | requestWIO_0_2 & - auto_out_2_w_ready | requestWIO_0_3 & auto_out_3_w_ready | requestWIO_0_4 & auto_out_4_w_ready; // @[Mux.scala 27:72] + auto_out_2_w_ready | requestWIO_0_3 & auto_out_3_w_ready | requestWIO_0_4 & auto_out_4_w_ready | requestWIO_0_5 & + auto_out_5_w_ready; // @[Mux.scala 27:72] wire out_0_ar_valid = auto_in_ar_valid & requestARIO_0_0; // @[Xbar.scala 229:40] wire out_1_ar_valid = auto_in_ar_valid & requestARIO_0_1; // @[Xbar.scala 229:40] wire out_2_ar_valid = auto_in_ar_valid & requestARIO_0_2; // @[Xbar.scala 229:40] wire out_3_ar_valid = auto_in_ar_valid & requestARIO_0_3; // @[Xbar.scala 229:40] wire out_4_ar_valid = auto_in_ar_valid & requestARIO_0_4; // @[Xbar.scala 229:40] + wire out_5_ar_valid = auto_in_ar_valid & requestARIO_0_5; // @[Xbar.scala 229:40] wire out_0_aw_valid = in_0_aw_valid & requestAWIO_0_0; // @[Xbar.scala 229:40] wire out_1_aw_valid = in_0_aw_valid & requestAWIO_0_1; // @[Xbar.scala 229:40] wire out_2_aw_valid = in_0_aw_valid & requestAWIO_0_2; // @[Xbar.scala 229:40] wire out_3_aw_valid = in_0_aw_valid & requestAWIO_0_3; // @[Xbar.scala 229:40] wire out_4_aw_valid = in_0_aw_valid & requestAWIO_0_4; // @[Xbar.scala 229:40] - wire _T_432 = ~out_0_aw_valid; // @[Xbar.scala 263:60] - wire _T_448 = ~out_0_ar_valid; // @[Xbar.scala 263:60] - wire _T_466 = ~out_1_aw_valid; // @[Xbar.scala 263:60] - wire _T_482 = ~out_1_ar_valid; // @[Xbar.scala 263:60] - wire _T_500 = ~out_2_aw_valid; // @[Xbar.scala 263:60] - wire _T_516 = ~out_2_ar_valid; // @[Xbar.scala 263:60] - wire _T_534 = ~out_3_aw_valid; // @[Xbar.scala 263:60] - wire _T_550 = ~out_3_ar_valid; // @[Xbar.scala 263:60] - wire _T_568 = ~out_4_aw_valid; // @[Xbar.scala 263:60] - wire _T_584 = ~out_4_ar_valid; // @[Xbar.scala 263:60] - wire [4:0] _T_626 = _T_623 & lo_12; // @[Arbiter.scala 28:29] - wire [5:0] _T_627 = {_T_626, 1'h0}; // @[package.scala 244:48] - wire [4:0] _T_629 = _T_626 | _T_627[4:0]; // @[package.scala 244:43] - wire [6:0] _T_630 = {_T_629, 2'h0}; // @[package.scala 244:48] - wire [4:0] _T_632 = _T_629 | _T_630[4:0]; // @[package.scala 244:43] - wire [8:0] _T_633 = {_T_632, 4'h0}; // @[package.scala 244:48] - wire [4:0] _T_635 = _T_632 | _T_633[4:0]; // @[package.scala 244:43] - wire _T_649 = _T_643 | _T_644; // @[Xbar.scala 262:50] - wire _T_650 = _T_643 | _T_644 | _T_645; // @[Xbar.scala 262:50] - wire _T_651 = _T_643 | _T_644 | _T_645 | _T_646; // @[Xbar.scala 262:50] - wire _T_652 = _T_643 | _T_644 | _T_645 | _T_646 | _T_647; // @[Xbar.scala 262:50] - wire _GEN_39 = _T_602 ? 1'h0 : REG_37; // @[Xbar.scala 273:21 Xbar.scala 273:28 Xbar.scala 249:23] - wire _GEN_40 = _T_145 | _GEN_39; // @[Xbar.scala 274:24 Xbar.scala 274:31] - wire _T_686_0 = REG_37 ? _T_623[0] : REG_39_0; // @[Xbar.scala 277:24] - wire _T_686_1 = REG_37 ? _T_623[1] : REG_39_1; // @[Xbar.scala 277:24] - wire _T_686_2 = REG_37 ? _T_623[2] : REG_39_2; // @[Xbar.scala 277:24] - wire _T_686_3 = REG_37 ? _T_623[3] : REG_39_3; // @[Xbar.scala 277:24] - wire _T_686_4 = REG_37 ? _T_623[4] : REG_39_4; // @[Xbar.scala 277:24] - wire [1:0] _T_711 = _T_684_0 ? auto_out_0_r_bits_resp : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_713 = _T_684_2 ? auto_out_2_r_bits_resp : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_714 = _T_684_3 ? auto_out_3_r_bits_resp : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_715 = _T_684_4 ? auto_out_4_r_bits_resp : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_717 = _T_711 | _T_713; // @[Mux.scala 27:72] - wire [1:0] _T_718 = _T_717 | _T_714; // @[Mux.scala 27:72] - wire [63:0] _T_720 = _T_684_0 ? auto_out_0_r_bits_data : 64'h0; // @[Mux.scala 27:72] - wire [63:0] _T_722 = _T_684_2 ? auto_out_2_r_bits_data : 64'h0; // @[Mux.scala 27:72] - wire [63:0] _T_723 = _T_684_3 ? auto_out_3_r_bits_data : 64'h0; // @[Mux.scala 27:72] - wire [63:0] _T_724 = _T_684_4 ? auto_out_4_r_bits_data : 64'h0; // @[Mux.scala 27:72] - wire [63:0] _T_726 = _T_720 | _T_722; // @[Mux.scala 27:72] - wire [63:0] _T_727 = _T_726 | _T_723; // @[Mux.scala 27:72] - wire [4:0] _T_765 = _T_762 & lo_14; // @[Arbiter.scala 28:29] - wire [5:0] _T_766 = {_T_765, 1'h0}; // @[package.scala 244:48] - wire [4:0] _T_768 = _T_765 | _T_766[4:0]; // @[package.scala 244:43] - wire [6:0] _T_769 = {_T_768, 2'h0}; // @[package.scala 244:48] - wire [4:0] _T_771 = _T_768 | _T_769[4:0]; // @[package.scala 244:43] - wire [8:0] _T_772 = {_T_771, 4'h0}; // @[package.scala 244:48] - wire [4:0] _T_774 = _T_771 | _T_772[4:0]; // @[package.scala 244:43] - wire _T_788 = _T_782 | _T_783; // @[Xbar.scala 262:50] - wire _T_789 = _T_782 | _T_783 | _T_784; // @[Xbar.scala 262:50] - wire _T_790 = _T_782 | _T_783 | _T_784 | _T_785; // @[Xbar.scala 262:50] - wire _T_791 = _T_782 | _T_783 | _T_784 | _T_785 | _T_786; // @[Xbar.scala 262:50] - wire _GEN_42 = _T_741 ? 1'h0 : REG_40; // @[Xbar.scala 273:21 Xbar.scala 273:28 Xbar.scala 249:23] - wire _GEN_43 = _T_173 | _GEN_42; // @[Xbar.scala 274:24 Xbar.scala 274:31] - wire _T_825_0 = REG_40 ? _T_762[0] : REG_42_0; // @[Xbar.scala 277:24] - wire _T_825_1 = REG_40 ? _T_762[1] : REG_42_1; // @[Xbar.scala 277:24] - wire _T_825_2 = REG_40 ? _T_762[2] : REG_42_2; // @[Xbar.scala 277:24] - wire _T_825_3 = REG_40 ? _T_762[3] : REG_42_3; // @[Xbar.scala 277:24] - wire _T_825_4 = REG_40 ? _T_762[4] : REG_42_4; // @[Xbar.scala 277:24] - wire [1:0] _T_841 = _T_823_0 ? auto_out_0_b_bits_resp : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_842 = _T_823_1 ? auto_out_1_b_bits_resp : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_843 = _T_823_2 ? auto_out_2_b_bits_resp : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_844 = _T_823_3 ? auto_out_3_b_bits_resp : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_845 = _T_823_4 ? auto_out_4_b_bits_resp : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_846 = _T_841 | _T_842; // @[Mux.scala 27:72] - wire [1:0] _T_847 = _T_846 | _T_843; // @[Mux.scala 27:72] - wire [1:0] _T_848 = _T_847 | _T_844; // @[Mux.scala 27:72] - QueueCompatibility_357 awIn_0 ( // @[Xbar.scala 62:47] + wire out_5_aw_valid = in_0_aw_valid & requestAWIO_0_5; // @[Xbar.scala 229:40] + wire _T_467 = ~out_0_aw_valid; // @[Xbar.scala 263:60] + wire _T_483 = ~out_0_ar_valid; // @[Xbar.scala 263:60] + wire _T_501 = ~out_1_aw_valid; // @[Xbar.scala 263:60] + wire _T_517 = ~out_1_ar_valid; // @[Xbar.scala 263:60] + wire _T_535 = ~out_2_aw_valid; // @[Xbar.scala 263:60] + wire _T_551 = ~out_2_ar_valid; // @[Xbar.scala 263:60] + wire _T_569 = ~out_3_aw_valid; // @[Xbar.scala 263:60] + wire _T_585 = ~out_3_ar_valid; // @[Xbar.scala 263:60] + wire _T_603 = ~out_4_aw_valid; // @[Xbar.scala 263:60] + wire _T_619 = ~out_4_ar_valid; // @[Xbar.scala 263:60] + wire _T_637 = ~out_5_aw_valid; // @[Xbar.scala 263:60] + wire _T_653 = ~out_5_ar_valid; // @[Xbar.scala 263:60] + wire [5:0] _T_696 = _T_693 & lo_12; // @[Arbiter.scala 28:29] + wire [6:0] _T_697 = {_T_696, 1'h0}; // @[package.scala 244:48] + wire [5:0] _T_699 = _T_696 | _T_697[5:0]; // @[package.scala 244:43] + wire [7:0] _T_700 = {_T_699, 2'h0}; // @[package.scala 244:48] + wire [5:0] _T_702 = _T_699 | _T_700[5:0]; // @[package.scala 244:43] + wire [9:0] _T_703 = {_T_702, 4'h0}; // @[package.scala 244:48] + wire [5:0] _T_705 = _T_702 | _T_703[5:0]; // @[package.scala 244:43] + wire _T_721 = _T_714 | _T_715; // @[Xbar.scala 262:50] + wire _T_722 = _T_714 | _T_715 | _T_716; // @[Xbar.scala 262:50] + wire _T_723 = _T_714 | _T_715 | _T_716 | _T_717; // @[Xbar.scala 262:50] + wire _T_724 = _T_714 | _T_715 | _T_716 | _T_717 | _T_718; // @[Xbar.scala 262:50] + wire _T_725 = _T_714 | _T_715 | _T_716 | _T_717 | _T_718 | _T_719; // @[Xbar.scala 262:50] + wire _GEN_43 = _T_672 ? 1'h0 : REG_41; // @[Xbar.scala 273:21 Xbar.scala 273:28 Xbar.scala 249:23] + wire _GEN_44 = _T_169 | _GEN_43; // @[Xbar.scala 274:24 Xbar.scala 274:31] + wire _T_764_0 = REG_41 ? _T_693[0] : REG_43_0; // @[Xbar.scala 277:24] + wire _T_764_1 = REG_41 ? _T_693[1] : REG_43_1; // @[Xbar.scala 277:24] + wire _T_764_2 = REG_41 ? _T_693[2] : REG_43_2; // @[Xbar.scala 277:24] + wire _T_764_3 = REG_41 ? _T_693[3] : REG_43_3; // @[Xbar.scala 277:24] + wire _T_764_4 = REG_41 ? _T_693[4] : REG_43_4; // @[Xbar.scala 277:24] + wire _T_764_5 = REG_41 ? _T_693[5] : REG_43_5; // @[Xbar.scala 277:24] + wire [1:0] _T_794 = _T_762_0 ? auto_out_0_r_bits_resp : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_796 = _T_762_2 ? auto_out_2_r_bits_resp : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_797 = _T_762_3 ? auto_out_3_r_bits_resp : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_798 = _T_762_4 ? auto_out_4_r_bits_resp : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_799 = _T_762_5 ? auto_out_5_r_bits_resp : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_801 = _T_794 | _T_796; // @[Mux.scala 27:72] + wire [1:0] _T_802 = _T_801 | _T_797; // @[Mux.scala 27:72] + wire [1:0] _T_803 = _T_802 | _T_798; // @[Mux.scala 27:72] + wire [63:0] _T_805 = _T_762_0 ? auto_out_0_r_bits_data : 64'h0; // @[Mux.scala 27:72] + wire [63:0] _T_807 = _T_762_2 ? auto_out_2_r_bits_data : 64'h0; // @[Mux.scala 27:72] + wire [63:0] _T_808 = _T_762_3 ? auto_out_3_r_bits_data : 64'h0; // @[Mux.scala 27:72] + wire [63:0] _T_809 = _T_762_4 ? auto_out_4_r_bits_data : 64'h0; // @[Mux.scala 27:72] + wire [63:0] _T_810 = _T_762_5 ? auto_out_5_r_bits_data : 64'h0; // @[Mux.scala 27:72] + wire [63:0] _T_812 = _T_805 | _T_807; // @[Mux.scala 27:72] + wire [63:0] _T_813 = _T_812 | _T_808; // @[Mux.scala 27:72] + wire [63:0] _T_814 = _T_813 | _T_809; // @[Mux.scala 27:72] + wire [5:0] _T_855 = _T_852 & lo_14; // @[Arbiter.scala 28:29] + wire [6:0] _T_856 = {_T_855, 1'h0}; // @[package.scala 244:48] + wire [5:0] _T_858 = _T_855 | _T_856[5:0]; // @[package.scala 244:43] + wire [7:0] _T_859 = {_T_858, 2'h0}; // @[package.scala 244:48] + wire [5:0] _T_861 = _T_858 | _T_859[5:0]; // @[package.scala 244:43] + wire [9:0] _T_862 = {_T_861, 4'h0}; // @[package.scala 244:48] + wire [5:0] _T_864 = _T_861 | _T_862[5:0]; // @[package.scala 244:43] + wire _T_880 = _T_873 | _T_874; // @[Xbar.scala 262:50] + wire _T_881 = _T_873 | _T_874 | _T_875; // @[Xbar.scala 262:50] + wire _T_882 = _T_873 | _T_874 | _T_875 | _T_876; // @[Xbar.scala 262:50] + wire _T_883 = _T_873 | _T_874 | _T_875 | _T_876 | _T_877; // @[Xbar.scala 262:50] + wire _T_884 = _T_873 | _T_874 | _T_875 | _T_876 | _T_877 | _T_878; // @[Xbar.scala 262:50] + wire _GEN_46 = _T_831 ? 1'h0 : REG_44; // @[Xbar.scala 273:21 Xbar.scala 273:28 Xbar.scala 249:23] + wire _GEN_47 = _T_197 | _GEN_46; // @[Xbar.scala 274:24 Xbar.scala 274:31] + wire _T_923_0 = REG_44 ? _T_852[0] : REG_46_0; // @[Xbar.scala 277:24] + wire _T_923_1 = REG_44 ? _T_852[1] : REG_46_1; // @[Xbar.scala 277:24] + wire _T_923_2 = REG_44 ? _T_852[2] : REG_46_2; // @[Xbar.scala 277:24] + wire _T_923_3 = REG_44 ? _T_852[3] : REG_46_3; // @[Xbar.scala 277:24] + wire _T_923_4 = REG_44 ? _T_852[4] : REG_46_4; // @[Xbar.scala 277:24] + wire _T_923_5 = REG_44 ? _T_852[5] : REG_46_5; // @[Xbar.scala 277:24] + wire [1:0] _T_942 = _T_921_0 ? auto_out_0_b_bits_resp : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_943 = _T_921_1 ? auto_out_1_b_bits_resp : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_944 = _T_921_2 ? auto_out_2_b_bits_resp : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_945 = _T_921_3 ? auto_out_3_b_bits_resp : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_946 = _T_921_4 ? auto_out_4_b_bits_resp : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_947 = _T_921_5 ? auto_out_5_b_bits_resp : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_948 = _T_942 | _T_943; // @[Mux.scala 27:72] + wire [1:0] _T_949 = _T_948 | _T_944; // @[Mux.scala 27:72] + wire [1:0] _T_950 = _T_949 | _T_945; // @[Mux.scala 27:72] + wire [1:0] _T_951 = _T_950 | _T_946; // @[Mux.scala 27:72] + QueueCompatibility_228 awIn_0 ( // @[Xbar.scala 62:47] .clock(awIn_0_clock), .reset(awIn_0_reset), .io_enq_ready(awIn_0_io_enq_ready), @@ -543,17 +623,45 @@ module AXI4Xbar_1( ); assign auto_in_aw_ready = in_0_aw_ready & (REG_16 | awIn_0_io_enq_ready); // @[Xbar.scala 146:45] assign auto_in_w_ready = in_0_w_ready & awIn_0_io_deq_valid; // @[Xbar.scala 153:43] - assign auto_in_b_valid = REG_40 ? _T_741 : _T_839; // @[Xbar.scala 285:22] - assign auto_in_b_bits_id = _T_857 | _T_854; // @[Mux.scala 27:72] - assign auto_in_b_bits_resp = _T_848 | _T_845; // @[Mux.scala 27:72] + assign auto_in_b_valid = REG_44 ? _T_831 : _T_940; // @[Xbar.scala 285:22] + assign auto_in_b_bits_id = _T_962 | _T_958; // @[Mux.scala 27:72] + assign auto_in_b_bits_resp = _T_951 | _T_947; // @[Mux.scala 27:72] assign auto_in_ar_ready = requestARIO_0_0 & auto_out_0_ar_ready | requestARIO_0_1 | requestARIO_0_2 & - auto_out_2_ar_ready | requestARIO_0_3 & auto_out_3_ar_ready | requestARIO_0_4 & auto_out_4_ar_ready; // @[Mux.scala 27:72] - assign auto_in_r_valid = REG_37 ? _T_602 : _T_700; // @[Xbar.scala 285:22] - assign auto_in_r_bits_id = _T_736 | _T_733; // @[Mux.scala 27:72] - assign auto_in_r_bits_data = _T_727 | _T_724; // @[Mux.scala 27:72] - assign auto_in_r_bits_resp = _T_718 | _T_715; // @[Mux.scala 27:72] - assign auto_in_r_bits_last = _T_684_0 & auto_out_0_r_bits_last | _T_684_1 & auto_out_1_r_bits_last | _T_684_2 & - auto_out_2_r_bits_last | _T_684_3 & auto_out_3_r_bits_last | _T_684_4 & auto_out_4_r_bits_last; // @[Mux.scala 27:72] + auto_out_2_ar_ready | requestARIO_0_3 & auto_out_3_ar_ready | requestARIO_0_4 & auto_out_4_ar_ready | + requestARIO_0_5 & auto_out_5_ar_ready; // @[Mux.scala 27:72] + assign auto_in_r_valid = REG_41 ? _T_672 : _T_781; // @[Xbar.scala 285:22] + assign auto_in_r_bits_id = _T_825 | _T_821; // @[Mux.scala 27:72] + assign auto_in_r_bits_data = _T_814 | _T_810; // @[Mux.scala 27:72] + assign auto_in_r_bits_resp = _T_803 | _T_799; // @[Mux.scala 27:72] + assign auto_in_r_bits_last = _T_762_0 & auto_out_0_r_bits_last | _T_762_1 & auto_out_1_r_bits_last | _T_762_2 & + auto_out_2_r_bits_last | _T_762_3 & auto_out_3_r_bits_last | _T_762_4 & auto_out_4_r_bits_last | _T_762_5 & + auto_out_5_r_bits_last; // @[Mux.scala 27:72] + assign auto_out_5_aw_valid = in_0_aw_valid & requestAWIO_0_5; // @[Xbar.scala 229:40] + assign auto_out_5_aw_bits_id = auto_in_aw_bits_id; // @[Xbar.scala 86:47] + assign auto_out_5_aw_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_aw_bits_len = auto_in_aw_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_aw_bits_size = auto_in_aw_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_aw_bits_burst = auto_in_aw_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_aw_bits_lock = auto_in_aw_bits_lock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_aw_bits_cache = auto_in_aw_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_aw_bits_prot = auto_in_aw_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_aw_bits_qos = auto_in_aw_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_w_valid = in_0_w_valid & requestWIO_0_5; // @[Xbar.scala 229:40] + assign auto_out_5_w_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_b_ready = auto_in_b_ready & _T_923_5; // @[Xbar.scala 279:31] + assign auto_out_5_ar_valid = auto_in_ar_valid & requestARIO_0_5; // @[Xbar.scala 229:40] + assign auto_out_5_ar_bits_id = auto_in_ar_bits_id; // @[Xbar.scala 87:47] + assign auto_out_5_ar_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_ar_bits_len = auto_in_ar_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_ar_bits_size = auto_in_ar_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_ar_bits_burst = auto_in_ar_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_ar_bits_lock = auto_in_ar_bits_lock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_ar_bits_cache = auto_in_ar_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_ar_bits_prot = auto_in_ar_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_ar_bits_qos = auto_in_ar_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] + assign auto_out_5_r_ready = auto_in_r_ready & _T_764_5; // @[Xbar.scala 279:31] assign auto_out_4_aw_valid = in_0_aw_valid & requestAWIO_0_4; // @[Xbar.scala 229:40] assign auto_out_4_aw_bits_id = auto_in_aw_bits_id; // @[Xbar.scala 86:47] assign auto_out_4_aw_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -568,7 +676,7 @@ module AXI4Xbar_1( assign auto_out_4_w_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_4_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_4_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - assign auto_out_4_b_ready = auto_in_b_ready & _T_825_4; // @[Xbar.scala 279:31] + assign auto_out_4_b_ready = auto_in_b_ready & _T_923_4; // @[Xbar.scala 279:31] assign auto_out_4_ar_valid = auto_in_ar_valid & requestARIO_0_4; // @[Xbar.scala 229:40] assign auto_out_4_ar_bits_id = auto_in_ar_bits_id; // @[Xbar.scala 87:47] assign auto_out_4_ar_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -579,7 +687,7 @@ module AXI4Xbar_1( assign auto_out_4_ar_bits_cache = auto_in_ar_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_4_ar_bits_prot = auto_in_ar_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_4_ar_bits_qos = auto_in_ar_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - assign auto_out_4_r_ready = auto_in_r_ready & _T_686_4; // @[Xbar.scala 279:31] + assign auto_out_4_r_ready = auto_in_r_ready & _T_764_4; // @[Xbar.scala 279:31] assign auto_out_3_aw_valid = in_0_aw_valid & requestAWIO_0_3; // @[Xbar.scala 229:40] assign auto_out_3_aw_bits_id = auto_in_aw_bits_id; // @[Xbar.scala 86:47] assign auto_out_3_aw_bits_addr = auto_in_aw_bits_addr[28:0]; // @[Nodes.scala 1207:84 BundleMap.scala 247:19] @@ -594,7 +702,7 @@ module AXI4Xbar_1( assign auto_out_3_w_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_3_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_3_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - assign auto_out_3_b_ready = auto_in_b_ready & _T_825_3; // @[Xbar.scala 279:31] + assign auto_out_3_b_ready = auto_in_b_ready & _T_923_3; // @[Xbar.scala 279:31] assign auto_out_3_ar_valid = auto_in_ar_valid & requestARIO_0_3; // @[Xbar.scala 229:40] assign auto_out_3_ar_bits_id = auto_in_ar_bits_id; // @[Xbar.scala 87:47] assign auto_out_3_ar_bits_addr = auto_in_ar_bits_addr[28:0]; // @[Nodes.scala 1207:84 BundleMap.scala 247:19] @@ -605,7 +713,7 @@ module AXI4Xbar_1( assign auto_out_3_ar_bits_cache = auto_in_ar_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_3_ar_bits_prot = auto_in_ar_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_3_ar_bits_qos = auto_in_ar_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - assign auto_out_3_r_ready = auto_in_r_ready & _T_686_3; // @[Xbar.scala 279:31] + assign auto_out_3_r_ready = auto_in_r_ready & _T_764_3; // @[Xbar.scala 279:31] assign auto_out_2_aw_valid = in_0_aw_valid & requestAWIO_0_2; // @[Xbar.scala 229:40] assign auto_out_2_aw_bits_id = auto_in_aw_bits_id; // @[Xbar.scala 86:47] assign auto_out_2_aw_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -620,7 +728,7 @@ module AXI4Xbar_1( assign auto_out_2_w_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_2_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_2_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - assign auto_out_2_b_ready = auto_in_b_ready & _T_825_2; // @[Xbar.scala 279:31] + assign auto_out_2_b_ready = auto_in_b_ready & _T_923_2; // @[Xbar.scala 279:31] assign auto_out_2_ar_valid = auto_in_ar_valid & requestARIO_0_2; // @[Xbar.scala 229:40] assign auto_out_2_ar_bits_id = auto_in_ar_bits_id; // @[Xbar.scala 87:47] assign auto_out_2_ar_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -631,7 +739,7 @@ module AXI4Xbar_1( assign auto_out_2_ar_bits_cache = auto_in_ar_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_2_ar_bits_prot = auto_in_ar_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_2_ar_bits_qos = auto_in_ar_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - assign auto_out_2_r_ready = auto_in_r_ready & _T_686_2; // @[Xbar.scala 279:31] + assign auto_out_2_r_ready = auto_in_r_ready & _T_764_2; // @[Xbar.scala 279:31] assign auto_out_1_aw_valid = in_0_aw_valid & requestAWIO_0_1; // @[Xbar.scala 229:40] assign auto_out_1_aw_bits_id = auto_in_aw_bits_id; // @[Xbar.scala 86:47] assign auto_out_1_aw_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -646,7 +754,7 @@ module AXI4Xbar_1( assign auto_out_1_w_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_1_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_1_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - assign auto_out_1_b_ready = auto_in_b_ready & _T_825_1; // @[Xbar.scala 279:31] + assign auto_out_1_b_ready = auto_in_b_ready & _T_923_1; // @[Xbar.scala 279:31] assign auto_out_1_ar_valid = auto_in_ar_valid & requestARIO_0_1; // @[Xbar.scala 229:40] assign auto_out_1_ar_bits_id = auto_in_ar_bits_id; // @[Xbar.scala 87:47] assign auto_out_1_ar_bits_len = auto_in_ar_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -655,7 +763,7 @@ module AXI4Xbar_1( assign auto_out_1_ar_bits_lock = auto_in_ar_bits_lock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_1_ar_bits_cache = auto_in_ar_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_1_ar_bits_qos = auto_in_ar_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - assign auto_out_1_r_ready = auto_in_r_ready & _T_686_1; // @[Xbar.scala 279:31] + assign auto_out_1_r_ready = auto_in_r_ready & _T_764_1; // @[Xbar.scala 279:31] assign auto_out_0_aw_valid = in_0_aw_valid & requestAWIO_0_0; // @[Xbar.scala 229:40] assign auto_out_0_aw_bits_id = auto_in_aw_bits_id; // @[Xbar.scala 86:47] assign auto_out_0_aw_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -670,7 +778,7 @@ module AXI4Xbar_1( assign auto_out_0_w_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_0_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_0_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - assign auto_out_0_b_ready = auto_in_b_ready & _T_825_0; // @[Xbar.scala 279:31] + assign auto_out_0_b_ready = auto_in_b_ready & _T_923_0; // @[Xbar.scala 279:31] assign auto_out_0_ar_valid = auto_in_ar_valid & requestARIO_0_0; // @[Xbar.scala 229:40] assign auto_out_0_ar_bits_id = auto_in_ar_bits_id; // @[Xbar.scala 87:47] assign auto_out_0_ar_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -681,98 +789,108 @@ module AXI4Xbar_1( assign auto_out_0_ar_bits_cache = auto_in_ar_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_0_ar_bits_prot = auto_in_ar_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] assign auto_out_0_ar_bits_qos = auto_in_ar_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - assign auto_out_0_r_ready = auto_in_r_ready & _T_686_0; // @[Xbar.scala 279:31] + assign auto_out_0_r_ready = auto_in_r_ready & _T_764_0; // @[Xbar.scala 279:31] assign awIn_0_clock = clock; assign awIn_0_reset = reset; assign awIn_0_io_enq_valid = auto_in_aw_valid & ~REG_16; // @[Xbar.scala 147:51] assign awIn_0_io_enq_bits = {hi,lo}; // @[Xbar.scala 71:75] assign awIn_0_io_deq_ready = auto_in_w_valid & auto_in_w_bits_last & in_0_w_ready; // @[Xbar.scala 154:74] always @(posedge clock) begin - REG_37 <= reset | _GEN_40; // @[Xbar.scala 249:23 Xbar.scala 249:23] + REG_41 <= reset | _GEN_44; // @[Xbar.scala 249:23 Xbar.scala 249:23] if (reset) begin // @[Arbiter.scala 23:23] - REG_38 <= 5'h1f; // @[Arbiter.scala 23:23] - end else if (REG_37 & |lo_12) begin // @[Arbiter.scala 27:32] - REG_38 <= _T_635; // @[Arbiter.scala 28:12] + REG_42 <= 6'h3f; // @[Arbiter.scala 23:23] + end else if (REG_41 & |lo_12) begin // @[Arbiter.scala 27:32] + REG_42 <= _T_705; // @[Arbiter.scala 28:12] end if (reset) begin // @[Xbar.scala 268:24] - REG_39_0 <= 1'h0; // @[Xbar.scala 268:24] - end else if (REG_37) begin // @[Xbar.scala 269:23] - REG_39_0 <= _T_643; + REG_43_0 <= 1'h0; // @[Xbar.scala 268:24] + end else if (REG_41) begin // @[Xbar.scala 269:23] + REG_43_0 <= _T_714; end if (reset) begin // @[Xbar.scala 268:24] - REG_39_1 <= 1'h0; // @[Xbar.scala 268:24] - end else if (REG_37) begin // @[Xbar.scala 269:23] - REG_39_1 <= _T_644; + REG_43_1 <= 1'h0; // @[Xbar.scala 268:24] + end else if (REG_41) begin // @[Xbar.scala 269:23] + REG_43_1 <= _T_715; end if (reset) begin // @[Xbar.scala 268:24] - REG_39_2 <= 1'h0; // @[Xbar.scala 268:24] - end else if (REG_37) begin // @[Xbar.scala 269:23] - REG_39_2 <= _T_645; + REG_43_2 <= 1'h0; // @[Xbar.scala 268:24] + end else if (REG_41) begin // @[Xbar.scala 269:23] + REG_43_2 <= _T_716; end if (reset) begin // @[Xbar.scala 268:24] - REG_39_3 <= 1'h0; // @[Xbar.scala 268:24] - end else if (REG_37) begin // @[Xbar.scala 269:23] - REG_39_3 <= _T_646; + REG_43_3 <= 1'h0; // @[Xbar.scala 268:24] + end else if (REG_41) begin // @[Xbar.scala 269:23] + REG_43_3 <= _T_717; end if (reset) begin // @[Xbar.scala 268:24] - REG_39_4 <= 1'h0; // @[Xbar.scala 268:24] - end else if (REG_37) begin // @[Xbar.scala 269:23] - REG_39_4 <= _T_647; + REG_43_4 <= 1'h0; // @[Xbar.scala 268:24] + end else if (REG_41) begin // @[Xbar.scala 269:23] + REG_43_4 <= _T_718; end - REG_40 <= reset | _GEN_43; // @[Xbar.scala 249:23 Xbar.scala 249:23] + if (reset) begin // @[Xbar.scala 268:24] + REG_43_5 <= 1'h0; // @[Xbar.scala 268:24] + end else if (REG_41) begin // @[Xbar.scala 269:23] + REG_43_5 <= _T_719; + end + REG_44 <= reset | _GEN_47; // @[Xbar.scala 249:23 Xbar.scala 249:23] if (reset) begin // @[Arbiter.scala 23:23] - REG_41 <= 5'h1f; // @[Arbiter.scala 23:23] - end else if (REG_40 & |lo_14) begin // @[Arbiter.scala 27:32] - REG_41 <= _T_774; // @[Arbiter.scala 28:12] + REG_45 <= 6'h3f; // @[Arbiter.scala 23:23] + end else if (REG_44 & |lo_14) begin // @[Arbiter.scala 27:32] + REG_45 <= _T_864; // @[Arbiter.scala 28:12] + end + if (reset) begin // @[Xbar.scala 268:24] + REG_46_0 <= 1'h0; // @[Xbar.scala 268:24] + end else if (REG_44) begin // @[Xbar.scala 269:23] + REG_46_0 <= _T_873; end if (reset) begin // @[Xbar.scala 268:24] - REG_42_0 <= 1'h0; // @[Xbar.scala 268:24] - end else if (REG_40) begin // @[Xbar.scala 269:23] - REG_42_0 <= _T_782; + REG_46_1 <= 1'h0; // @[Xbar.scala 268:24] + end else if (REG_44) begin // @[Xbar.scala 269:23] + REG_46_1 <= _T_874; end if (reset) begin // @[Xbar.scala 268:24] - REG_42_1 <= 1'h0; // @[Xbar.scala 268:24] - end else if (REG_40) begin // @[Xbar.scala 269:23] - REG_42_1 <= _T_783; + REG_46_2 <= 1'h0; // @[Xbar.scala 268:24] + end else if (REG_44) begin // @[Xbar.scala 269:23] + REG_46_2 <= _T_875; end if (reset) begin // @[Xbar.scala 268:24] - REG_42_2 <= 1'h0; // @[Xbar.scala 268:24] - end else if (REG_40) begin // @[Xbar.scala 269:23] - REG_42_2 <= _T_784; + REG_46_3 <= 1'h0; // @[Xbar.scala 268:24] + end else if (REG_44) begin // @[Xbar.scala 269:23] + REG_46_3 <= _T_876; end if (reset) begin // @[Xbar.scala 268:24] - REG_42_3 <= 1'h0; // @[Xbar.scala 268:24] - end else if (REG_40) begin // @[Xbar.scala 269:23] - REG_42_3 <= _T_785; + REG_46_4 <= 1'h0; // @[Xbar.scala 268:24] + end else if (REG_44) begin // @[Xbar.scala 269:23] + REG_46_4 <= _T_877; end if (reset) begin // @[Xbar.scala 268:24] - REG_42_4 <= 1'h0; // @[Xbar.scala 268:24] - end else if (REG_40) begin // @[Xbar.scala 269:23] - REG_42_4 <= _T_786; + REG_46_5 <= 1'h0; // @[Xbar.scala 268:24] + end else if (REG_44) begin // @[Xbar.scala 269:23] + REG_46_5 <= _T_878; end if (reset) begin // @[Xbar.scala 111:34] REG_12 <= 1'h0; // @[Xbar.scala 111:34] end else begin - REG_12 <= _T_314 - _T_312; // @[Xbar.scala 113:21] + REG_12 <= _T_338 - _T_336; // @[Xbar.scala 113:21] end if (reset) begin // @[Xbar.scala 111:34] REG_8 <= 1'h0; // @[Xbar.scala 111:34] end else begin - REG_8 <= _T_259 - _T_257; // @[Xbar.scala 113:21] + REG_8 <= _T_283 - _T_281; // @[Xbar.scala 113:21] end if (reset) begin // @[Xbar.scala 111:34] REG_4 <= 1'h0; // @[Xbar.scala 111:34] end else begin - REG_4 <= _T_204 - _T_202; // @[Xbar.scala 113:21] + REG_4 <= _T_228 - _T_226; // @[Xbar.scala 113:21] end if (reset) begin // @[Xbar.scala 111:34] REG <= 1'h0; // @[Xbar.scala 111:34] end else begin - REG <= _T_149 - _T_147; // @[Xbar.scala 113:21] + REG <= _T_173 - _T_171; // @[Xbar.scala 113:21] end if (reset) begin // @[Xbar.scala 144:30] REG_16 <= 1'h0; // @[Xbar.scala 144:30] - end else if (_T_372) begin // @[Xbar.scala 149:32] + end else if (_T_396) begin // @[Xbar.scala 149:32] REG_16 <= 1'h0; // @[Xbar.scala 149:42] end else begin REG_16 <= _GEN_16; @@ -780,28 +898,28 @@ module AXI4Xbar_1( if (reset) begin // @[Xbar.scala 111:34] REG_14 <= 1'h0; // @[Xbar.scala 111:34] end else begin - REG_14 <= _T_341 - _T_339; // @[Xbar.scala 113:21] + REG_14 <= _T_365 - _T_363; // @[Xbar.scala 113:21] end if (reset) begin // @[Xbar.scala 111:34] REG_10 <= 1'h0; // @[Xbar.scala 111:34] end else begin - REG_10 <= _T_286 - _T_284; // @[Xbar.scala 113:21] + REG_10 <= _T_310 - _T_308; // @[Xbar.scala 113:21] end if (reset) begin // @[Xbar.scala 111:34] REG_6 <= 1'h0; // @[Xbar.scala 111:34] end else begin - REG_6 <= _T_231 - _T_229; // @[Xbar.scala 113:21] + REG_6 <= _T_255 - _T_253; // @[Xbar.scala 113:21] end if (reset) begin // @[Xbar.scala 111:34] REG_2 <= 1'h0; // @[Xbar.scala 111:34] end else begin - REG_2 <= _T_176 - _T_174; // @[Xbar.scala 113:21] + REG_2 <= _T_200 - _T_198; // @[Xbar.scala 113:21] end `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_147 | REG | reset)) begin + if (~(~_T_171 | REG | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:114 assert (!resp_fire || count =/= UInt(0))\n"); // @[Xbar.scala 114:22] end `ifdef PRINTF_COND @@ -809,21 +927,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_147 | REG | reset)) begin - $fatal; // @[Xbar.scala 114:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_143 | _T_164 | reset)) begin + if (~(~_T_167 | _T_188 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:115 assert (!req_fire || count =/= UInt(flight))\n" ); // @[Xbar.scala 115:22] end @@ -832,21 +939,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_143 | _T_164 | reset)) begin - $fatal; // @[Xbar.scala 115:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_174 | REG_2 | reset)) begin + if (~(~_T_198 | REG_2 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:114 assert (!resp_fire || count =/= UInt(0))\n"); // @[Xbar.scala 114:22] end `ifdef PRINTF_COND @@ -854,21 +950,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_174 | REG_2 | reset)) begin - $fatal; // @[Xbar.scala 114:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_171 | _T_191 | reset)) begin + if (~(~_T_195 | _T_215 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:115 assert (!req_fire || count =/= UInt(flight))\n" ); // @[Xbar.scala 115:22] end @@ -877,21 +962,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_171 | _T_191 | reset)) begin - $fatal; // @[Xbar.scala 115:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_202 | REG_4 | reset)) begin + if (~(~_T_226 | REG_4 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:114 assert (!resp_fire || count =/= UInt(0))\n"); // @[Xbar.scala 114:22] end `ifdef PRINTF_COND @@ -899,21 +973,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_202 | REG_4 | reset)) begin - $fatal; // @[Xbar.scala 114:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_198 | _T_219 | reset)) begin + if (~(~_T_222 | _T_243 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:115 assert (!req_fire || count =/= UInt(flight))\n" ); // @[Xbar.scala 115:22] end @@ -922,21 +985,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_198 | _T_219 | reset)) begin - $fatal; // @[Xbar.scala 115:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_229 | REG_6 | reset)) begin + if (~(~_T_253 | REG_6 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:114 assert (!resp_fire || count =/= UInt(0))\n"); // @[Xbar.scala 114:22] end `ifdef PRINTF_COND @@ -944,21 +996,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_229 | REG_6 | reset)) begin - $fatal; // @[Xbar.scala 114:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_226 | _T_246 | reset)) begin + if (~(~_T_250 | _T_270 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:115 assert (!req_fire || count =/= UInt(flight))\n" ); // @[Xbar.scala 115:22] end @@ -967,21 +1008,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_226 | _T_246 | reset)) begin - $fatal; // @[Xbar.scala 115:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_257 | REG_8 | reset)) begin + if (~(~_T_281 | REG_8 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:114 assert (!resp_fire || count =/= UInt(0))\n"); // @[Xbar.scala 114:22] end `ifdef PRINTF_COND @@ -989,21 +1019,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_257 | REG_8 | reset)) begin - $fatal; // @[Xbar.scala 114:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_253 | _T_274 | reset)) begin + if (~(~_T_277 | _T_298 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:115 assert (!req_fire || count =/= UInt(flight))\n" ); // @[Xbar.scala 115:22] end @@ -1012,21 +1031,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_253 | _T_274 | reset)) begin - $fatal; // @[Xbar.scala 115:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_284 | REG_10 | reset)) begin + if (~(~_T_308 | REG_10 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:114 assert (!resp_fire || count =/= UInt(0))\n"); // @[Xbar.scala 114:22] end `ifdef PRINTF_COND @@ -1034,21 +1042,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_284 | REG_10 | reset)) begin - $fatal; // @[Xbar.scala 114:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_281 | _T_301 | reset)) begin + if (~(~_T_305 | _T_325 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:115 assert (!req_fire || count =/= UInt(flight))\n" ); // @[Xbar.scala 115:22] end @@ -1057,21 +1054,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_281 | _T_301 | reset)) begin - $fatal; // @[Xbar.scala 115:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_312 | REG_12 | reset)) begin + if (~(~_T_336 | REG_12 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:114 assert (!resp_fire || count =/= UInt(0))\n"); // @[Xbar.scala 114:22] end `ifdef PRINTF_COND @@ -1079,21 +1065,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_312 | REG_12 | reset)) begin - $fatal; // @[Xbar.scala 114:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_308 | _T_329 | reset)) begin + if (~(~_T_332 | _T_353 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:115 assert (!req_fire || count =/= UInt(flight))\n" ); // @[Xbar.scala 115:22] end @@ -1102,21 +1077,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_308 | _T_329 | reset)) begin - $fatal; // @[Xbar.scala 115:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_339 | REG_14 | reset)) begin + if (~(~_T_363 | REG_14 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:114 assert (!resp_fire || count =/= UInt(0))\n"); // @[Xbar.scala 114:22] end `ifdef PRINTF_COND @@ -1124,21 +1088,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_339 | REG_14 | reset)) begin - $fatal; // @[Xbar.scala 114:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_336 | _T_356 | reset)) begin + if (~(~_T_360 | _T_380 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:115 assert (!req_fire || count =/= UInt(flight))\n" ); // @[Xbar.scala 115:22] end @@ -1147,21 +1100,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_336 | _T_356 | reset)) begin - $fatal; // @[Xbar.scala 115:22] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(_T_432 | out_0_aw_valid | reset)) begin + if (~(_T_467 | out_0_aw_valid | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12] end `ifdef PRINTF_COND @@ -1169,21 +1111,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(_T_432 | out_0_aw_valid | reset)) begin - $fatal; // @[Xbar.scala 265:12] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(_T_448 | out_0_ar_valid | reset)) begin + if (~(_T_483 | out_0_ar_valid | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12] end `ifdef PRINTF_COND @@ -1191,21 +1122,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(_T_448 | out_0_ar_valid | reset)) begin - $fatal; // @[Xbar.scala 265:12] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(_T_466 | out_1_aw_valid | reset)) begin + if (~(_T_501 | out_1_aw_valid | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12] end `ifdef PRINTF_COND @@ -1213,21 +1133,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(_T_466 | out_1_aw_valid | reset)) begin - $fatal; // @[Xbar.scala 265:12] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(_T_482 | out_1_ar_valid | reset)) begin + if (~(_T_517 | out_1_ar_valid | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12] end `ifdef PRINTF_COND @@ -1235,21 +1144,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(_T_482 | out_1_ar_valid | reset)) begin - $fatal; // @[Xbar.scala 265:12] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(_T_500 | out_2_aw_valid | reset)) begin + if (~(_T_535 | out_2_aw_valid | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12] end `ifdef PRINTF_COND @@ -1257,21 +1155,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(_T_500 | out_2_aw_valid | reset)) begin - $fatal; // @[Xbar.scala 265:12] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(_T_516 | out_2_ar_valid | reset)) begin + if (~(_T_551 | out_2_ar_valid | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12] end `ifdef PRINTF_COND @@ -1279,21 +1166,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(_T_516 | out_2_ar_valid | reset)) begin - $fatal; // @[Xbar.scala 265:12] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(_T_534 | out_3_aw_valid | reset)) begin + if (~(_T_569 | out_3_aw_valid | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12] end `ifdef PRINTF_COND @@ -1301,21 +1177,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(_T_534 | out_3_aw_valid | reset)) begin - $fatal; // @[Xbar.scala 265:12] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(_T_550 | out_3_ar_valid | reset)) begin + if (~(_T_585 | out_3_ar_valid | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12] end `ifdef PRINTF_COND @@ -1323,21 +1188,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(_T_550 | out_3_ar_valid | reset)) begin - $fatal; // @[Xbar.scala 265:12] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(_T_568 | out_4_aw_valid | reset)) begin + if (~(_T_603 | out_4_aw_valid | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12] end `ifdef PRINTF_COND @@ -1345,13 +1199,13 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin + `ifdef PRINTF_COND + if (`PRINTF_COND) begin `endif - if (~(_T_568 | out_4_aw_valid | reset)) begin - $fatal; // @[Xbar.scala 265:12] + if (~(_T_619 | out_4_ar_valid | reset)) begin + $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12] end - `ifdef STOP_COND + `ifdef PRINTF_COND end `endif `endif // SYNTHESIS @@ -1359,7 +1213,7 @@ module AXI4Xbar_1( `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(_T_584 | out_4_ar_valid | reset)) begin + if (~(_T_637 | out_5_aw_valid | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12] end `ifdef PRINTF_COND @@ -1367,13 +1221,13 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin + `ifdef PRINTF_COND + if (`PRINTF_COND) begin `endif - if (~(_T_584 | out_4_ar_valid | reset)) begin - $fatal; // @[Xbar.scala 265:12] + if (~(_T_653 | out_5_ar_valid | reset)) begin + $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12] end - `ifdef STOP_COND + `ifdef PRINTF_COND end `endif `endif // SYNTHESIS @@ -1381,7 +1235,8 @@ module AXI4Xbar_1( `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~((~_T_643 | ~_T_644) & (~_T_649 | ~_T_645) & (~_T_650 | ~_T_646) & (~_T_651 | ~_T_647) | reset)) begin + if (~((~_T_714 | ~_T_715) & (~_T_721 | ~_T_716) & (~_T_722 | ~_T_717) & (~_T_723 | ~_T_718) & (~_T_724 | ~_T_719 + ) | reset)) begin $fwrite(32'h80000002, "Assertion failed\n at Xbar.scala:263 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n" ); // @[Xbar.scala 263:11] @@ -1391,21 +1246,10 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~((~_T_643 | ~_T_644) & (~_T_649 | ~_T_645) & (~_T_650 | ~_T_646) & (~_T_651 | ~_T_647) | reset)) begin - $fatal; // @[Xbar.scala 263:11] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_602 | _T_652 | reset)) begin + if (~(~_T_672 | _T_725 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12] end `ifdef PRINTF_COND @@ -1413,21 +1257,11 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_602 | _T_652 | reset)) begin - $fatal; // @[Xbar.scala 265:12] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~((~_T_782 | ~_T_783) & (~_T_788 | ~_T_784) & (~_T_789 | ~_T_785) & (~_T_790 | ~_T_786) | reset)) begin + if (~((~_T_873 | ~_T_874) & (~_T_880 | ~_T_875) & (~_T_881 | ~_T_876) & (~_T_882 | ~_T_877) & (~_T_883 | ~_T_878 + ) | reset)) begin $fwrite(32'h80000002, "Assertion failed\n at Xbar.scala:263 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n" ); // @[Xbar.scala 263:11] @@ -1437,38 +1271,16 @@ module AXI4Xbar_1( `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~((~_T_782 | ~_T_783) & (~_T_788 | ~_T_784) & (~_T_789 | ~_T_785) & (~_T_790 | ~_T_786) | reset)) begin - $fatal; // @[Xbar.scala 263:11] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif - if (~(~_T_741 | _T_791 | reset)) begin + if (~(~_T_831 | _T_884 | reset)) begin $fwrite(32'h80000002,"Assertion failed\n at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS - `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (~(~_T_741 | _T_791 | reset)) begin - $fatal; // @[Xbar.scala 265:12] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS end // Register and memory initialization `ifdef RANDOMIZE_GARBAGE_ASSIGN @@ -1507,51 +1319,55 @@ initial begin `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; - REG_37 = _RAND_0[0:0]; + REG_41 = _RAND_0[0:0]; _RAND_1 = {1{`RANDOM}}; - REG_38 = _RAND_1[4:0]; + REG_42 = _RAND_1[5:0]; _RAND_2 = {1{`RANDOM}}; - REG_39_0 = _RAND_2[0:0]; + REG_43_0 = _RAND_2[0:0]; _RAND_3 = {1{`RANDOM}}; - REG_39_1 = _RAND_3[0:0]; + REG_43_1 = _RAND_3[0:0]; _RAND_4 = {1{`RANDOM}}; - REG_39_2 = _RAND_4[0:0]; + REG_43_2 = _RAND_4[0:0]; _RAND_5 = {1{`RANDOM}}; - REG_39_3 = _RAND_5[0:0]; + REG_43_3 = _RAND_5[0:0]; _RAND_6 = {1{`RANDOM}}; - REG_39_4 = _RAND_6[0:0]; + REG_43_4 = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - REG_40 = _RAND_7[0:0]; + REG_43_5 = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; - REG_41 = _RAND_8[4:0]; + REG_44 = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; - REG_42_0 = _RAND_9[0:0]; + REG_45 = _RAND_9[5:0]; _RAND_10 = {1{`RANDOM}}; - REG_42_1 = _RAND_10[0:0]; + REG_46_0 = _RAND_10[0:0]; _RAND_11 = {1{`RANDOM}}; - REG_42_2 = _RAND_11[0:0]; + REG_46_1 = _RAND_11[0:0]; _RAND_12 = {1{`RANDOM}}; - REG_42_3 = _RAND_12[0:0]; + REG_46_2 = _RAND_12[0:0]; _RAND_13 = {1{`RANDOM}}; - REG_42_4 = _RAND_13[0:0]; + REG_46_3 = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; - REG_12 = _RAND_14[0:0]; + REG_46_4 = _RAND_14[0:0]; _RAND_15 = {1{`RANDOM}}; - REG_8 = _RAND_15[0:0]; + REG_46_5 = _RAND_15[0:0]; _RAND_16 = {1{`RANDOM}}; - REG_4 = _RAND_16[0:0]; + REG_12 = _RAND_16[0:0]; _RAND_17 = {1{`RANDOM}}; - REG = _RAND_17[0:0]; + REG_8 = _RAND_17[0:0]; _RAND_18 = {1{`RANDOM}}; - REG_16 = _RAND_18[0:0]; + REG_4 = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - REG_14 = _RAND_19[0:0]; + REG = _RAND_19[0:0]; _RAND_20 = {1{`RANDOM}}; - REG_10 = _RAND_20[0:0]; + REG_16 = _RAND_20[0:0]; _RAND_21 = {1{`RANDOM}}; - REG_6 = _RAND_21[0:0]; + REG_14 = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - REG_2 = _RAND_22[0:0]; + REG_10 = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + REG_6 = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + REG_2 = _RAND_24[0:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end // initial @@ -1560,3 +1376,4 @@ end // initial `endif `endif // SYNTHESIS endmodule + diff --git a/vcs/testbench/SimMMIO/FlashHelper.v b/vcs/testbench/SimMMIO/FlashHelper.v new file mode 100644 index 0000000..5a6ca67 --- /dev/null +++ b/vcs/testbench/SimMMIO/FlashHelper.v @@ -0,0 +1,18 @@ +import "DPI-C" function void flash_read +( + input int addr, + output longint data +); +module FlashHelper ( + input clk, + input [31:0] addr, + input ren, + output reg [63:0] data +); + + always @(posedge clk) begin + if (ren) flash_read(addr, data); + end + +endmodule + diff --git a/vcs/testbench/SimMMIO/QueueCompatibility_357.v b/vcs/testbench/SimMMIO/QueueCompatibility_222.v similarity index 93% rename from vcs/testbench/SimMMIO/QueueCompatibility_357.v rename to vcs/testbench/SimMMIO/QueueCompatibility_222.v index dd1016c..2de9624 100644 --- a/vcs/testbench/SimMMIO/QueueCompatibility_357.v +++ b/vcs/testbench/SimMMIO/QueueCompatibility_222.v @@ -1,12 +1,12 @@ -module QueueCompatibility_357( +module QueueCompatibility_222( input clock, input reset, output io_enq_ready, input io_enq_valid, - input [4:0] io_enq_bits, + input [5:0] io_enq_bits, input io_deq_ready, output io_deq_valid, - output [4:0] io_deq_bits + output [5:0] io_deq_bits ); `ifdef RANDOMIZE_MEM_INIT reg [31:0] _RAND_0; @@ -16,10 +16,10 @@ module QueueCompatibility_357( reg [31:0] _RAND_2; reg [31:0] _RAND_3; `endif // RANDOMIZE_REG_INIT - reg [4:0] ram [0:1]; // @[Decoupled.scala 218:16] - wire [4:0] ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 218:16] + reg [5:0] ram [0:1]; // @[Decoupled.scala 218:16] + wire [5:0] ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 218:16] wire ram_io_deq_bits_MPORT_addr; // @[Decoupled.scala 218:16] - wire [4:0] ram_MPORT_data; // @[Decoupled.scala 218:16] + wire [5:0] ram_MPORT_data; // @[Decoupled.scala 218:16] wire ram_MPORT_addr; // @[Decoupled.scala 218:16] wire ram_MPORT_mask; // @[Decoupled.scala 218:16] wire ram_MPORT_en; // @[Decoupled.scala 218:16] @@ -109,7 +109,7 @@ initial begin `ifdef RANDOMIZE_MEM_INIT _RAND_0 = {1{`RANDOM}}; for (initvar = 0; initvar < 2; initvar = initvar+1) - ram[initvar] = _RAND_0[4:0]; + ram[initvar] = _RAND_0[5:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; @@ -126,3 +126,4 @@ end // initial `endif `endif // SYNTHESIS endmodule + diff --git a/vcs/testbench/SimMMIO/QueueCompatibility_228.v b/vcs/testbench/SimMMIO/QueueCompatibility_228.v new file mode 100644 index 0000000..54e4f65 --- /dev/null +++ b/vcs/testbench/SimMMIO/QueueCompatibility_228.v @@ -0,0 +1,129 @@ +module QueueCompatibility_228( + input clock, + input reset, + output io_enq_ready, + input io_enq_valid, + input [5:0] io_enq_bits, + input io_deq_ready, + output io_deq_valid, + output [5:0] io_deq_bits +); +`ifdef RANDOMIZE_MEM_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_MEM_INIT +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; +`endif // RANDOMIZE_REG_INIT + reg [5:0] ram [0:1]; // @[Decoupled.scala 218:16] + wire [5:0] ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 218:16] + wire ram_io_deq_bits_MPORT_addr; // @[Decoupled.scala 218:16] + wire [5:0] ram_MPORT_data; // @[Decoupled.scala 218:16] + wire ram_MPORT_addr; // @[Decoupled.scala 218:16] + wire ram_MPORT_mask; // @[Decoupled.scala 218:16] + wire ram_MPORT_en; // @[Decoupled.scala 218:16] + reg enq_ptr_value; // @[Counter.scala 60:40] + reg deq_ptr_value; // @[Counter.scala 60:40] + reg maybe_full; // @[Decoupled.scala 221:27] + wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 223:33] + wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 224:25] + wire full = ptr_match & maybe_full; // @[Decoupled.scala 225:24] + wire _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 40:37] + wire _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 40:37] + wire _GEN_9 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 249:27 Decoupled.scala 249:36] + wire do_enq = empty ? _GEN_9 : _do_enq_T; // @[Decoupled.scala 246:18] + wire do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 246:18 Decoupled.scala 248:14] + assign ram_io_deq_bits_MPORT_addr = deq_ptr_value; + assign ram_io_deq_bits_MPORT_data = ram[ram_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 218:16] + assign ram_MPORT_data = io_enq_bits; + assign ram_MPORT_addr = enq_ptr_value; + assign ram_MPORT_mask = 1'h1; + assign ram_MPORT_en = empty ? _GEN_9 : _do_enq_T; + assign io_enq_ready = ~full; // @[Decoupled.scala 241:19] + assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 245:25 Decoupled.scala 245:40 Decoupled.scala 240:16] + assign io_deq_bits = empty ? io_enq_bits : ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 246:18 Decoupled.scala 247:19 Decoupled.scala 242:15] + always @(posedge clock) begin + if(ram_MPORT_en & ram_MPORT_mask) begin + ram[ram_MPORT_addr] <= ram_MPORT_data; // @[Decoupled.scala 218:16] + end + if (reset) begin // @[Counter.scala 60:40] + enq_ptr_value <= 1'h0; // @[Counter.scala 60:40] + end else if (do_enq) begin // @[Decoupled.scala 229:17] + enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 76:15] + end + if (reset) begin // @[Counter.scala 60:40] + deq_ptr_value <= 1'h0; // @[Counter.scala 60:40] + end else if (do_deq) begin // @[Decoupled.scala 233:17] + deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 76:15] + end + if (reset) begin // @[Decoupled.scala 221:27] + maybe_full <= 1'h0; // @[Decoupled.scala 221:27] + end else if (do_enq != do_deq) begin // @[Decoupled.scala 236:28] + if (empty) begin // @[Decoupled.scala 246:18] + if (io_deq_ready) begin // @[Decoupled.scala 249:27] + maybe_full <= 1'h0; // @[Decoupled.scala 249:36] + end else begin + maybe_full <= _do_enq_T; + end + end else begin + maybe_full <= _do_enq_T; + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_MEM_INIT + _RAND_0 = {1{`RANDOM}}; + for (initvar = 0; initvar < 2; initvar = initvar+1) + ram[initvar] = _RAND_0[5:0]; +`endif // RANDOMIZE_MEM_INIT +`ifdef RANDOMIZE_REG_INIT + _RAND_1 = {1{`RANDOM}}; + enq_ptr_value = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + deq_ptr_value = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + maybe_full = _RAND_3[0:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule + diff --git a/vcs/testbench/SimMMIO/SDHelper.v b/vcs/testbench/SimMMIO/SDHelper.v index 517c62e..8c12b98 100644 --- a/vcs/testbench/SimMMIO/SDHelper.v +++ b/vcs/testbench/SimMMIO/SDHelper.v @@ -16,3 +16,4 @@ module SDHelper ( end endmodule + diff --git a/vcs/testbench/SimMMIO/SimMMIO.v b/vcs/testbench/SimMMIO/SimMMIO.v index 72004a8..68cef52 100644 --- a/vcs/testbench/SimMMIO/SimMMIO.v +++ b/vcs/testbench/SimMMIO/SimMMIO.v @@ -1,240 +1,281 @@ module SimMMIO( - input clock, - input reset, - output auto_axi4xbar_in_aw_ready, - input auto_axi4xbar_in_aw_valid, - input [1:0] auto_axi4xbar_in_aw_bits_id, - input [30:0] auto_axi4xbar_in_aw_bits_addr, - input [7:0] auto_axi4xbar_in_aw_bits_len, - input [2:0] auto_axi4xbar_in_aw_bits_size, - input [1:0] auto_axi4xbar_in_aw_bits_burst, - input auto_axi4xbar_in_aw_bits_lock, - input [3:0] auto_axi4xbar_in_aw_bits_cache, - input [2:0] auto_axi4xbar_in_aw_bits_prot, - input [3:0] auto_axi4xbar_in_aw_bits_qos, - output auto_axi4xbar_in_w_ready, - input auto_axi4xbar_in_w_valid, - input [63:0] auto_axi4xbar_in_w_bits_data, - input [7:0] auto_axi4xbar_in_w_bits_strb, - input auto_axi4xbar_in_w_bits_last, - input auto_axi4xbar_in_b_ready, - output auto_axi4xbar_in_b_valid, - output [1:0] auto_axi4xbar_in_b_bits_id, - output [1:0] auto_axi4xbar_in_b_bits_resp, - output auto_axi4xbar_in_ar_ready, - input auto_axi4xbar_in_ar_valid, - input [1:0] auto_axi4xbar_in_ar_bits_id, - input [30:0] auto_axi4xbar_in_ar_bits_addr, - input [7:0] auto_axi4xbar_in_ar_bits_len, - input [2:0] auto_axi4xbar_in_ar_bits_size, - input [1:0] auto_axi4xbar_in_ar_bits_burst, - input auto_axi4xbar_in_ar_bits_lock, - input [3:0] auto_axi4xbar_in_ar_bits_cache, - input [2:0] auto_axi4xbar_in_ar_bits_prot, - input [3:0] auto_axi4xbar_in_ar_bits_qos, - input auto_axi4xbar_in_r_ready, - output auto_axi4xbar_in_r_valid, - output [1:0] auto_axi4xbar_in_r_bits_id, - output [63:0] auto_axi4xbar_in_r_bits_data, - output [1:0] auto_axi4xbar_in_r_bits_resp, - output auto_axi4xbar_in_r_bits_last, - output io_uart_out_valid, - output [7:0] io_uart_out_ch, - output io_uart_in_valid, - input [7:0] io_uart_in_ch + input clock, + input reset, + output io_axi4_0_aw_ready, + input io_axi4_0_aw_valid, + input [1:0] io_axi4_0_aw_bits_id, + input [30:0] io_axi4_0_aw_bits_addr, + input [7:0] io_axi4_0_aw_bits_len, + input [2:0] io_axi4_0_aw_bits_size, + input [1:0] io_axi4_0_aw_bits_burst, + input io_axi4_0_aw_bits_lock, + input [3:0] io_axi4_0_aw_bits_cache, + input [2:0] io_axi4_0_aw_bits_prot, + input [3:0] io_axi4_0_aw_bits_qos, + output io_axi4_0_w_ready, + input io_axi4_0_w_valid, + input [63:0] io_axi4_0_w_bits_data, + input [7:0] io_axi4_0_w_bits_strb, + input io_axi4_0_w_bits_last, + input io_axi4_0_b_ready, + output io_axi4_0_b_valid, + output [1:0] io_axi4_0_b_bits_id, + output [1:0] io_axi4_0_b_bits_resp, + output io_axi4_0_ar_ready, + input io_axi4_0_ar_valid, + input [1:0] io_axi4_0_ar_bits_id, + input [30:0] io_axi4_0_ar_bits_addr, + input [7:0] io_axi4_0_ar_bits_len, + input [2:0] io_axi4_0_ar_bits_size, + input [1:0] io_axi4_0_ar_bits_burst, + input io_axi4_0_ar_bits_lock, + input [3:0] io_axi4_0_ar_bits_cache, + input [2:0] io_axi4_0_ar_bits_prot, + input [3:0] io_axi4_0_ar_bits_qos, + input io_axi4_0_r_ready, + output io_axi4_0_r_valid, + output [1:0] io_axi4_0_r_bits_id, + output [63:0] io_axi4_0_r_bits_data, + output [1:0] io_axi4_0_r_bits_resp, + output io_axi4_0_r_bits_last, + output io_uart_out_valid, + output [7:0] io_uart_out_ch, + output io_uart_in_valid, + input [7:0] io_uart_in_ch, + output [255:0] io_interrupt_intrVec ); - wire flash_clock; // @[SimMMIO.scala 11:25] - wire flash_reset; // @[SimMMIO.scala 11:25] - wire flash_auto_in_aw_ready; // @[SimMMIO.scala 11:25] - wire flash_auto_in_aw_valid; // @[SimMMIO.scala 11:25] - wire [1:0] flash_auto_in_aw_bits_id; // @[SimMMIO.scala 11:25] - wire [28:0] flash_auto_in_aw_bits_addr; // @[SimMMIO.scala 11:25] - wire [7:0] flash_auto_in_aw_bits_len; // @[SimMMIO.scala 11:25] - wire [2:0] flash_auto_in_aw_bits_size; // @[SimMMIO.scala 11:25] - wire [1:0] flash_auto_in_aw_bits_burst; // @[SimMMIO.scala 11:25] - wire flash_auto_in_aw_bits_lock; // @[SimMMIO.scala 11:25] - wire [3:0] flash_auto_in_aw_bits_cache; // @[SimMMIO.scala 11:25] - wire [2:0] flash_auto_in_aw_bits_prot; // @[SimMMIO.scala 11:25] - wire [3:0] flash_auto_in_aw_bits_qos; // @[SimMMIO.scala 11:25] - wire flash_auto_in_w_ready; // @[SimMMIO.scala 11:25] - wire flash_auto_in_w_valid; // @[SimMMIO.scala 11:25] - wire [63:0] flash_auto_in_w_bits_data; // @[SimMMIO.scala 11:25] - wire [7:0] flash_auto_in_w_bits_strb; // @[SimMMIO.scala 11:25] - wire flash_auto_in_w_bits_last; // @[SimMMIO.scala 11:25] - wire flash_auto_in_b_ready; // @[SimMMIO.scala 11:25] - wire flash_auto_in_b_valid; // @[SimMMIO.scala 11:25] - wire [1:0] flash_auto_in_b_bits_id; // @[SimMMIO.scala 11:25] - wire [1:0] flash_auto_in_b_bits_resp; // @[SimMMIO.scala 11:25] - wire flash_auto_in_ar_ready; // @[SimMMIO.scala 11:25] - wire flash_auto_in_ar_valid; // @[SimMMIO.scala 11:25] - wire [1:0] flash_auto_in_ar_bits_id; // @[SimMMIO.scala 11:25] - wire [28:0] flash_auto_in_ar_bits_addr; // @[SimMMIO.scala 11:25] - wire [7:0] flash_auto_in_ar_bits_len; // @[SimMMIO.scala 11:25] - wire [2:0] flash_auto_in_ar_bits_size; // @[SimMMIO.scala 11:25] - wire [1:0] flash_auto_in_ar_bits_burst; // @[SimMMIO.scala 11:25] - wire flash_auto_in_ar_bits_lock; // @[SimMMIO.scala 11:25] - wire [3:0] flash_auto_in_ar_bits_cache; // @[SimMMIO.scala 11:25] - wire [2:0] flash_auto_in_ar_bits_prot; // @[SimMMIO.scala 11:25] - wire [3:0] flash_auto_in_ar_bits_qos; // @[SimMMIO.scala 11:25] - wire flash_auto_in_r_ready; // @[SimMMIO.scala 11:25] - wire flash_auto_in_r_valid; // @[SimMMIO.scala 11:25] - wire [1:0] flash_auto_in_r_bits_id; // @[SimMMIO.scala 11:25] - wire [63:0] flash_auto_in_r_bits_data; // @[SimMMIO.scala 11:25] - wire [1:0] flash_auto_in_r_bits_resp; // @[SimMMIO.scala 11:25] - wire flash_auto_in_r_bits_last; // @[SimMMIO.scala 11:25] - wire uart_clock; // @[SimMMIO.scala 12:24] - wire uart_reset; // @[SimMMIO.scala 12:24] - wire uart_auto_in_aw_ready; // @[SimMMIO.scala 12:24] - wire uart_auto_in_aw_valid; // @[SimMMIO.scala 12:24] - wire [1:0] uart_auto_in_aw_bits_id; // @[SimMMIO.scala 12:24] - wire [30:0] uart_auto_in_aw_bits_addr; // @[SimMMIO.scala 12:24] - wire [7:0] uart_auto_in_aw_bits_len; // @[SimMMIO.scala 12:24] - wire [2:0] uart_auto_in_aw_bits_size; // @[SimMMIO.scala 12:24] - wire [1:0] uart_auto_in_aw_bits_burst; // @[SimMMIO.scala 12:24] - wire uart_auto_in_aw_bits_lock; // @[SimMMIO.scala 12:24] - wire [3:0] uart_auto_in_aw_bits_cache; // @[SimMMIO.scala 12:24] - wire [2:0] uart_auto_in_aw_bits_prot; // @[SimMMIO.scala 12:24] - wire [3:0] uart_auto_in_aw_bits_qos; // @[SimMMIO.scala 12:24] - wire uart_auto_in_w_ready; // @[SimMMIO.scala 12:24] - wire uart_auto_in_w_valid; // @[SimMMIO.scala 12:24] - wire [63:0] uart_auto_in_w_bits_data; // @[SimMMIO.scala 12:24] - wire [7:0] uart_auto_in_w_bits_strb; // @[SimMMIO.scala 12:24] - wire uart_auto_in_w_bits_last; // @[SimMMIO.scala 12:24] - wire uart_auto_in_b_ready; // @[SimMMIO.scala 12:24] - wire uart_auto_in_b_valid; // @[SimMMIO.scala 12:24] - wire [1:0] uart_auto_in_b_bits_id; // @[SimMMIO.scala 12:24] - wire [1:0] uart_auto_in_b_bits_resp; // @[SimMMIO.scala 12:24] - wire uart_auto_in_ar_ready; // @[SimMMIO.scala 12:24] - wire uart_auto_in_ar_valid; // @[SimMMIO.scala 12:24] - wire [1:0] uart_auto_in_ar_bits_id; // @[SimMMIO.scala 12:24] - wire [30:0] uart_auto_in_ar_bits_addr; // @[SimMMIO.scala 12:24] - wire [7:0] uart_auto_in_ar_bits_len; // @[SimMMIO.scala 12:24] - wire [2:0] uart_auto_in_ar_bits_size; // @[SimMMIO.scala 12:24] - wire [1:0] uart_auto_in_ar_bits_burst; // @[SimMMIO.scala 12:24] - wire uart_auto_in_ar_bits_lock; // @[SimMMIO.scala 12:24] - wire [3:0] uart_auto_in_ar_bits_cache; // @[SimMMIO.scala 12:24] - wire [2:0] uart_auto_in_ar_bits_prot; // @[SimMMIO.scala 12:24] - wire [3:0] uart_auto_in_ar_bits_qos; // @[SimMMIO.scala 12:24] - wire uart_auto_in_r_ready; // @[SimMMIO.scala 12:24] - wire uart_auto_in_r_valid; // @[SimMMIO.scala 12:24] - wire [1:0] uart_auto_in_r_bits_id; // @[SimMMIO.scala 12:24] - wire [63:0] uart_auto_in_r_bits_data; // @[SimMMIO.scala 12:24] - wire [1:0] uart_auto_in_r_bits_resp; // @[SimMMIO.scala 12:24] - wire uart_auto_in_r_bits_last; // @[SimMMIO.scala 12:24] - wire uart_io_extra_out_valid; // @[SimMMIO.scala 12:24] - wire [7:0] uart_io_extra_out_ch; // @[SimMMIO.scala 12:24] - wire uart_io_extra_in_valid; // @[SimMMIO.scala 12:24] - wire [7:0] uart_io_extra_in_ch; // @[SimMMIO.scala 12:24] - wire vga_clock; // @[SimMMIO.scala 13:23] - wire vga_reset; // @[SimMMIO.scala 13:23] - wire vga_auto_in_1_aw_ready; // @[SimMMIO.scala 13:23] - wire vga_auto_in_1_aw_valid; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_1_aw_bits_id; // @[SimMMIO.scala 13:23] - wire [30:0] vga_auto_in_1_aw_bits_addr; // @[SimMMIO.scala 13:23] - wire [7:0] vga_auto_in_1_aw_bits_len; // @[SimMMIO.scala 13:23] - wire [2:0] vga_auto_in_1_aw_bits_size; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_1_aw_bits_burst; // @[SimMMIO.scala 13:23] - wire vga_auto_in_1_aw_bits_lock; // @[SimMMIO.scala 13:23] - wire [3:0] vga_auto_in_1_aw_bits_cache; // @[SimMMIO.scala 13:23] - wire [2:0] vga_auto_in_1_aw_bits_prot; // @[SimMMIO.scala 13:23] - wire [3:0] vga_auto_in_1_aw_bits_qos; // @[SimMMIO.scala 13:23] - wire vga_auto_in_1_w_ready; // @[SimMMIO.scala 13:23] - wire vga_auto_in_1_w_valid; // @[SimMMIO.scala 13:23] - wire [63:0] vga_auto_in_1_w_bits_data; // @[SimMMIO.scala 13:23] - wire [7:0] vga_auto_in_1_w_bits_strb; // @[SimMMIO.scala 13:23] - wire vga_auto_in_1_w_bits_last; // @[SimMMIO.scala 13:23] - wire vga_auto_in_1_b_ready; // @[SimMMIO.scala 13:23] - wire vga_auto_in_1_b_valid; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_1_b_bits_id; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_1_b_bits_resp; // @[SimMMIO.scala 13:23] - wire vga_auto_in_1_ar_ready; // @[SimMMIO.scala 13:23] - wire vga_auto_in_1_ar_valid; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_1_ar_bits_id; // @[SimMMIO.scala 13:23] - wire [30:0] vga_auto_in_1_ar_bits_addr; // @[SimMMIO.scala 13:23] - wire [7:0] vga_auto_in_1_ar_bits_len; // @[SimMMIO.scala 13:23] - wire [2:0] vga_auto_in_1_ar_bits_size; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_1_ar_bits_burst; // @[SimMMIO.scala 13:23] - wire vga_auto_in_1_ar_bits_lock; // @[SimMMIO.scala 13:23] - wire [3:0] vga_auto_in_1_ar_bits_cache; // @[SimMMIO.scala 13:23] - wire [2:0] vga_auto_in_1_ar_bits_prot; // @[SimMMIO.scala 13:23] - wire [3:0] vga_auto_in_1_ar_bits_qos; // @[SimMMIO.scala 13:23] - wire vga_auto_in_1_r_ready; // @[SimMMIO.scala 13:23] - wire vga_auto_in_1_r_valid; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_1_r_bits_id; // @[SimMMIO.scala 13:23] - wire [63:0] vga_auto_in_1_r_bits_data; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_1_r_bits_resp; // @[SimMMIO.scala 13:23] - wire vga_auto_in_1_r_bits_last; // @[SimMMIO.scala 13:23] - wire vga_auto_in_0_aw_ready; // @[SimMMIO.scala 13:23] - wire vga_auto_in_0_aw_valid; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_0_aw_bits_id; // @[SimMMIO.scala 13:23] - wire [30:0] vga_auto_in_0_aw_bits_addr; // @[SimMMIO.scala 13:23] - wire [7:0] vga_auto_in_0_aw_bits_len; // @[SimMMIO.scala 13:23] - wire [2:0] vga_auto_in_0_aw_bits_size; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_0_aw_bits_burst; // @[SimMMIO.scala 13:23] - wire vga_auto_in_0_aw_bits_lock; // @[SimMMIO.scala 13:23] - wire [3:0] vga_auto_in_0_aw_bits_cache; // @[SimMMIO.scala 13:23] - wire [2:0] vga_auto_in_0_aw_bits_prot; // @[SimMMIO.scala 13:23] - wire [3:0] vga_auto_in_0_aw_bits_qos; // @[SimMMIO.scala 13:23] - wire vga_auto_in_0_w_ready; // @[SimMMIO.scala 13:23] - wire vga_auto_in_0_w_valid; // @[SimMMIO.scala 13:23] - wire [63:0] vga_auto_in_0_w_bits_data; // @[SimMMIO.scala 13:23] - wire [7:0] vga_auto_in_0_w_bits_strb; // @[SimMMIO.scala 13:23] - wire vga_auto_in_0_w_bits_last; // @[SimMMIO.scala 13:23] - wire vga_auto_in_0_b_ready; // @[SimMMIO.scala 13:23] - wire vga_auto_in_0_b_valid; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_0_b_bits_id; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_0_b_bits_resp; // @[SimMMIO.scala 13:23] - wire vga_auto_in_0_ar_valid; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_0_ar_bits_id; // @[SimMMIO.scala 13:23] - wire [7:0] vga_auto_in_0_ar_bits_len; // @[SimMMIO.scala 13:23] - wire [2:0] vga_auto_in_0_ar_bits_size; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_0_ar_bits_burst; // @[SimMMIO.scala 13:23] - wire vga_auto_in_0_ar_bits_lock; // @[SimMMIO.scala 13:23] - wire [3:0] vga_auto_in_0_ar_bits_cache; // @[SimMMIO.scala 13:23] - wire [3:0] vga_auto_in_0_ar_bits_qos; // @[SimMMIO.scala 13:23] - wire vga_auto_in_0_r_ready; // @[SimMMIO.scala 13:23] - wire vga_auto_in_0_r_valid; // @[SimMMIO.scala 13:23] - wire [1:0] vga_auto_in_0_r_bits_id; // @[SimMMIO.scala 13:23] - wire vga_auto_in_0_r_bits_last; // @[SimMMIO.scala 13:23] - wire sd_clock; // @[SimMMIO.scala 18:22] - wire sd_reset; // @[SimMMIO.scala 18:22] - wire sd_auto_in_aw_ready; // @[SimMMIO.scala 18:22] - wire sd_auto_in_aw_valid; // @[SimMMIO.scala 18:22] - wire [1:0] sd_auto_in_aw_bits_id; // @[SimMMIO.scala 18:22] - wire [30:0] sd_auto_in_aw_bits_addr; // @[SimMMIO.scala 18:22] - wire [7:0] sd_auto_in_aw_bits_len; // @[SimMMIO.scala 18:22] - wire [2:0] sd_auto_in_aw_bits_size; // @[SimMMIO.scala 18:22] - wire [1:0] sd_auto_in_aw_bits_burst; // @[SimMMIO.scala 18:22] - wire sd_auto_in_aw_bits_lock; // @[SimMMIO.scala 18:22] - wire [3:0] sd_auto_in_aw_bits_cache; // @[SimMMIO.scala 18:22] - wire [2:0] sd_auto_in_aw_bits_prot; // @[SimMMIO.scala 18:22] - wire [3:0] sd_auto_in_aw_bits_qos; // @[SimMMIO.scala 18:22] - wire sd_auto_in_w_ready; // @[SimMMIO.scala 18:22] - wire sd_auto_in_w_valid; // @[SimMMIO.scala 18:22] - wire [63:0] sd_auto_in_w_bits_data; // @[SimMMIO.scala 18:22] - wire [7:0] sd_auto_in_w_bits_strb; // @[SimMMIO.scala 18:22] - wire sd_auto_in_w_bits_last; // @[SimMMIO.scala 18:22] - wire sd_auto_in_b_ready; // @[SimMMIO.scala 18:22] - wire sd_auto_in_b_valid; // @[SimMMIO.scala 18:22] - wire [1:0] sd_auto_in_b_bits_id; // @[SimMMIO.scala 18:22] - wire [1:0] sd_auto_in_b_bits_resp; // @[SimMMIO.scala 18:22] - wire sd_auto_in_ar_ready; // @[SimMMIO.scala 18:22] - wire sd_auto_in_ar_valid; // @[SimMMIO.scala 18:22] - wire [1:0] sd_auto_in_ar_bits_id; // @[SimMMIO.scala 18:22] - wire [30:0] sd_auto_in_ar_bits_addr; // @[SimMMIO.scala 18:22] - wire [7:0] sd_auto_in_ar_bits_len; // @[SimMMIO.scala 18:22] - wire [2:0] sd_auto_in_ar_bits_size; // @[SimMMIO.scala 18:22] - wire [1:0] sd_auto_in_ar_bits_burst; // @[SimMMIO.scala 18:22] - wire sd_auto_in_ar_bits_lock; // @[SimMMIO.scala 18:22] - wire [3:0] sd_auto_in_ar_bits_cache; // @[SimMMIO.scala 18:22] - wire [2:0] sd_auto_in_ar_bits_prot; // @[SimMMIO.scala 18:22] - wire [3:0] sd_auto_in_ar_bits_qos; // @[SimMMIO.scala 18:22] - wire sd_auto_in_r_ready; // @[SimMMIO.scala 18:22] - wire sd_auto_in_r_valid; // @[SimMMIO.scala 18:22] - wire [1:0] sd_auto_in_r_bits_id; // @[SimMMIO.scala 18:22] - wire [63:0] sd_auto_in_r_bits_data; // @[SimMMIO.scala 18:22] - wire [1:0] sd_auto_in_r_bits_resp; // @[SimMMIO.scala 18:22] - wire sd_auto_in_r_bits_last; // @[SimMMIO.scala 18:22] + wire flash_clock; // @[SimMMIO.scala 13:25] + wire flash_reset; // @[SimMMIO.scala 13:25] + wire flash_auto_in_aw_ready; // @[SimMMIO.scala 13:25] + wire flash_auto_in_aw_valid; // @[SimMMIO.scala 13:25] + wire [1:0] flash_auto_in_aw_bits_id; // @[SimMMIO.scala 13:25] + wire [28:0] flash_auto_in_aw_bits_addr; // @[SimMMIO.scala 13:25] + wire [7:0] flash_auto_in_aw_bits_len; // @[SimMMIO.scala 13:25] + wire [2:0] flash_auto_in_aw_bits_size; // @[SimMMIO.scala 13:25] + wire [1:0] flash_auto_in_aw_bits_burst; // @[SimMMIO.scala 13:25] + wire flash_auto_in_aw_bits_lock; // @[SimMMIO.scala 13:25] + wire [3:0] flash_auto_in_aw_bits_cache; // @[SimMMIO.scala 13:25] + wire [2:0] flash_auto_in_aw_bits_prot; // @[SimMMIO.scala 13:25] + wire [3:0] flash_auto_in_aw_bits_qos; // @[SimMMIO.scala 13:25] + wire flash_auto_in_w_ready; // @[SimMMIO.scala 13:25] + wire flash_auto_in_w_valid; // @[SimMMIO.scala 13:25] + wire [63:0] flash_auto_in_w_bits_data; // @[SimMMIO.scala 13:25] + wire [7:0] flash_auto_in_w_bits_strb; // @[SimMMIO.scala 13:25] + wire flash_auto_in_w_bits_last; // @[SimMMIO.scala 13:25] + wire flash_auto_in_b_ready; // @[SimMMIO.scala 13:25] + wire flash_auto_in_b_valid; // @[SimMMIO.scala 13:25] + wire [1:0] flash_auto_in_b_bits_id; // @[SimMMIO.scala 13:25] + wire [1:0] flash_auto_in_b_bits_resp; // @[SimMMIO.scala 13:25] + wire flash_auto_in_ar_ready; // @[SimMMIO.scala 13:25] + wire flash_auto_in_ar_valid; // @[SimMMIO.scala 13:25] + wire [1:0] flash_auto_in_ar_bits_id; // @[SimMMIO.scala 13:25] + wire [28:0] flash_auto_in_ar_bits_addr; // @[SimMMIO.scala 13:25] + wire [7:0] flash_auto_in_ar_bits_len; // @[SimMMIO.scala 13:25] + wire [2:0] flash_auto_in_ar_bits_size; // @[SimMMIO.scala 13:25] + wire [1:0] flash_auto_in_ar_bits_burst; // @[SimMMIO.scala 13:25] + wire flash_auto_in_ar_bits_lock; // @[SimMMIO.scala 13:25] + wire [3:0] flash_auto_in_ar_bits_cache; // @[SimMMIO.scala 13:25] + wire [2:0] flash_auto_in_ar_bits_prot; // @[SimMMIO.scala 13:25] + wire [3:0] flash_auto_in_ar_bits_qos; // @[SimMMIO.scala 13:25] + wire flash_auto_in_r_ready; // @[SimMMIO.scala 13:25] + wire flash_auto_in_r_valid; // @[SimMMIO.scala 13:25] + wire [1:0] flash_auto_in_r_bits_id; // @[SimMMIO.scala 13:25] + wire [63:0] flash_auto_in_r_bits_data; // @[SimMMIO.scala 13:25] + wire [1:0] flash_auto_in_r_bits_resp; // @[SimMMIO.scala 13:25] + wire flash_auto_in_r_bits_last; // @[SimMMIO.scala 13:25] + wire uart_clock; // @[SimMMIO.scala 14:24] + wire uart_reset; // @[SimMMIO.scala 14:24] + wire uart_auto_in_aw_ready; // @[SimMMIO.scala 14:24] + wire uart_auto_in_aw_valid; // @[SimMMIO.scala 14:24] + wire [1:0] uart_auto_in_aw_bits_id; // @[SimMMIO.scala 14:24] + wire [30:0] uart_auto_in_aw_bits_addr; // @[SimMMIO.scala 14:24] + wire [7:0] uart_auto_in_aw_bits_len; // @[SimMMIO.scala 14:24] + wire [2:0] uart_auto_in_aw_bits_size; // @[SimMMIO.scala 14:24] + wire [1:0] uart_auto_in_aw_bits_burst; // @[SimMMIO.scala 14:24] + wire uart_auto_in_aw_bits_lock; // @[SimMMIO.scala 14:24] + wire [3:0] uart_auto_in_aw_bits_cache; // @[SimMMIO.scala 14:24] + wire [2:0] uart_auto_in_aw_bits_prot; // @[SimMMIO.scala 14:24] + wire [3:0] uart_auto_in_aw_bits_qos; // @[SimMMIO.scala 14:24] + wire uart_auto_in_w_ready; // @[SimMMIO.scala 14:24] + wire uart_auto_in_w_valid; // @[SimMMIO.scala 14:24] + wire [63:0] uart_auto_in_w_bits_data; // @[SimMMIO.scala 14:24] + wire [7:0] uart_auto_in_w_bits_strb; // @[SimMMIO.scala 14:24] + wire uart_auto_in_w_bits_last; // @[SimMMIO.scala 14:24] + wire uart_auto_in_b_ready; // @[SimMMIO.scala 14:24] + wire uart_auto_in_b_valid; // @[SimMMIO.scala 14:24] + wire [1:0] uart_auto_in_b_bits_id; // @[SimMMIO.scala 14:24] + wire [1:0] uart_auto_in_b_bits_resp; // @[SimMMIO.scala 14:24] + wire uart_auto_in_ar_ready; // @[SimMMIO.scala 14:24] + wire uart_auto_in_ar_valid; // @[SimMMIO.scala 14:24] + wire [1:0] uart_auto_in_ar_bits_id; // @[SimMMIO.scala 14:24] + wire [30:0] uart_auto_in_ar_bits_addr; // @[SimMMIO.scala 14:24] + wire [7:0] uart_auto_in_ar_bits_len; // @[SimMMIO.scala 14:24] + wire [2:0] uart_auto_in_ar_bits_size; // @[SimMMIO.scala 14:24] + wire [1:0] uart_auto_in_ar_bits_burst; // @[SimMMIO.scala 14:24] + wire uart_auto_in_ar_bits_lock; // @[SimMMIO.scala 14:24] + wire [3:0] uart_auto_in_ar_bits_cache; // @[SimMMIO.scala 14:24] + wire [2:0] uart_auto_in_ar_bits_prot; // @[SimMMIO.scala 14:24] + wire [3:0] uart_auto_in_ar_bits_qos; // @[SimMMIO.scala 14:24] + wire uart_auto_in_r_ready; // @[SimMMIO.scala 14:24] + wire uart_auto_in_r_valid; // @[SimMMIO.scala 14:24] + wire [1:0] uart_auto_in_r_bits_id; // @[SimMMIO.scala 14:24] + wire [63:0] uart_auto_in_r_bits_data; // @[SimMMIO.scala 14:24] + wire [1:0] uart_auto_in_r_bits_resp; // @[SimMMIO.scala 14:24] + wire uart_auto_in_r_bits_last; // @[SimMMIO.scala 14:24] + wire uart_io_extra_out_valid; // @[SimMMIO.scala 14:24] + wire [7:0] uart_io_extra_out_ch; // @[SimMMIO.scala 14:24] + wire uart_io_extra_in_valid; // @[SimMMIO.scala 14:24] + wire [7:0] uart_io_extra_in_ch; // @[SimMMIO.scala 14:24] + wire vga_clock; // @[SimMMIO.scala 15:23] + wire vga_reset; // @[SimMMIO.scala 15:23] + wire vga_auto_in_1_aw_ready; // @[SimMMIO.scala 15:23] + wire vga_auto_in_1_aw_valid; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_1_aw_bits_id; // @[SimMMIO.scala 15:23] + wire [30:0] vga_auto_in_1_aw_bits_addr; // @[SimMMIO.scala 15:23] + wire [7:0] vga_auto_in_1_aw_bits_len; // @[SimMMIO.scala 15:23] + wire [2:0] vga_auto_in_1_aw_bits_size; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_1_aw_bits_burst; // @[SimMMIO.scala 15:23] + wire vga_auto_in_1_aw_bits_lock; // @[SimMMIO.scala 15:23] + wire [3:0] vga_auto_in_1_aw_bits_cache; // @[SimMMIO.scala 15:23] + wire [2:0] vga_auto_in_1_aw_bits_prot; // @[SimMMIO.scala 15:23] + wire [3:0] vga_auto_in_1_aw_bits_qos; // @[SimMMIO.scala 15:23] + wire vga_auto_in_1_w_ready; // @[SimMMIO.scala 15:23] + wire vga_auto_in_1_w_valid; // @[SimMMIO.scala 15:23] + wire [63:0] vga_auto_in_1_w_bits_data; // @[SimMMIO.scala 15:23] + wire [7:0] vga_auto_in_1_w_bits_strb; // @[SimMMIO.scala 15:23] + wire vga_auto_in_1_w_bits_last; // @[SimMMIO.scala 15:23] + wire vga_auto_in_1_b_ready; // @[SimMMIO.scala 15:23] + wire vga_auto_in_1_b_valid; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_1_b_bits_id; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_1_b_bits_resp; // @[SimMMIO.scala 15:23] + wire vga_auto_in_1_ar_ready; // @[SimMMIO.scala 15:23] + wire vga_auto_in_1_ar_valid; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_1_ar_bits_id; // @[SimMMIO.scala 15:23] + wire [30:0] vga_auto_in_1_ar_bits_addr; // @[SimMMIO.scala 15:23] + wire [7:0] vga_auto_in_1_ar_bits_len; // @[SimMMIO.scala 15:23] + wire [2:0] vga_auto_in_1_ar_bits_size; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_1_ar_bits_burst; // @[SimMMIO.scala 15:23] + wire vga_auto_in_1_ar_bits_lock; // @[SimMMIO.scala 15:23] + wire [3:0] vga_auto_in_1_ar_bits_cache; // @[SimMMIO.scala 15:23] + wire [2:0] vga_auto_in_1_ar_bits_prot; // @[SimMMIO.scala 15:23] + wire [3:0] vga_auto_in_1_ar_bits_qos; // @[SimMMIO.scala 15:23] + wire vga_auto_in_1_r_ready; // @[SimMMIO.scala 15:23] + wire vga_auto_in_1_r_valid; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_1_r_bits_id; // @[SimMMIO.scala 15:23] + wire [63:0] vga_auto_in_1_r_bits_data; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_1_r_bits_resp; // @[SimMMIO.scala 15:23] + wire vga_auto_in_1_r_bits_last; // @[SimMMIO.scala 15:23] + wire vga_auto_in_0_aw_ready; // @[SimMMIO.scala 15:23] + wire vga_auto_in_0_aw_valid; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_0_aw_bits_id; // @[SimMMIO.scala 15:23] + wire [30:0] vga_auto_in_0_aw_bits_addr; // @[SimMMIO.scala 15:23] + wire [7:0] vga_auto_in_0_aw_bits_len; // @[SimMMIO.scala 15:23] + wire [2:0] vga_auto_in_0_aw_bits_size; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_0_aw_bits_burst; // @[SimMMIO.scala 15:23] + wire vga_auto_in_0_aw_bits_lock; // @[SimMMIO.scala 15:23] + wire [3:0] vga_auto_in_0_aw_bits_cache; // @[SimMMIO.scala 15:23] + wire [2:0] vga_auto_in_0_aw_bits_prot; // @[SimMMIO.scala 15:23] + wire [3:0] vga_auto_in_0_aw_bits_qos; // @[SimMMIO.scala 15:23] + wire vga_auto_in_0_w_ready; // @[SimMMIO.scala 15:23] + wire vga_auto_in_0_w_valid; // @[SimMMIO.scala 15:23] + wire [63:0] vga_auto_in_0_w_bits_data; // @[SimMMIO.scala 15:23] + wire [7:0] vga_auto_in_0_w_bits_strb; // @[SimMMIO.scala 15:23] + wire vga_auto_in_0_w_bits_last; // @[SimMMIO.scala 15:23] + wire vga_auto_in_0_b_ready; // @[SimMMIO.scala 15:23] + wire vga_auto_in_0_b_valid; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_0_b_bits_id; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_0_b_bits_resp; // @[SimMMIO.scala 15:23] + wire vga_auto_in_0_ar_valid; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_0_ar_bits_id; // @[SimMMIO.scala 15:23] + wire [7:0] vga_auto_in_0_ar_bits_len; // @[SimMMIO.scala 15:23] + wire [2:0] vga_auto_in_0_ar_bits_size; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_0_ar_bits_burst; // @[SimMMIO.scala 15:23] + wire vga_auto_in_0_ar_bits_lock; // @[SimMMIO.scala 15:23] + wire [3:0] vga_auto_in_0_ar_bits_cache; // @[SimMMIO.scala 15:23] + wire [3:0] vga_auto_in_0_ar_bits_qos; // @[SimMMIO.scala 15:23] + wire vga_auto_in_0_r_ready; // @[SimMMIO.scala 15:23] + wire vga_auto_in_0_r_valid; // @[SimMMIO.scala 15:23] + wire [1:0] vga_auto_in_0_r_bits_id; // @[SimMMIO.scala 15:23] + wire vga_auto_in_0_r_bits_last; // @[SimMMIO.scala 15:23] + wire sd_clock; // @[SimMMIO.scala 20:22] + wire sd_reset; // @[SimMMIO.scala 20:22] + wire sd_auto_in_aw_ready; // @[SimMMIO.scala 20:22] + wire sd_auto_in_aw_valid; // @[SimMMIO.scala 20:22] + wire [1:0] sd_auto_in_aw_bits_id; // @[SimMMIO.scala 20:22] + wire [30:0] sd_auto_in_aw_bits_addr; // @[SimMMIO.scala 20:22] + wire [7:0] sd_auto_in_aw_bits_len; // @[SimMMIO.scala 20:22] + wire [2:0] sd_auto_in_aw_bits_size; // @[SimMMIO.scala 20:22] + wire [1:0] sd_auto_in_aw_bits_burst; // @[SimMMIO.scala 20:22] + wire sd_auto_in_aw_bits_lock; // @[SimMMIO.scala 20:22] + wire [3:0] sd_auto_in_aw_bits_cache; // @[SimMMIO.scala 20:22] + wire [2:0] sd_auto_in_aw_bits_prot; // @[SimMMIO.scala 20:22] + wire [3:0] sd_auto_in_aw_bits_qos; // @[SimMMIO.scala 20:22] + wire sd_auto_in_w_ready; // @[SimMMIO.scala 20:22] + wire sd_auto_in_w_valid; // @[SimMMIO.scala 20:22] + wire [63:0] sd_auto_in_w_bits_data; // @[SimMMIO.scala 20:22] + wire [7:0] sd_auto_in_w_bits_strb; // @[SimMMIO.scala 20:22] + wire sd_auto_in_w_bits_last; // @[SimMMIO.scala 20:22] + wire sd_auto_in_b_ready; // @[SimMMIO.scala 20:22] + wire sd_auto_in_b_valid; // @[SimMMIO.scala 20:22] + wire [1:0] sd_auto_in_b_bits_id; // @[SimMMIO.scala 20:22] + wire [1:0] sd_auto_in_b_bits_resp; // @[SimMMIO.scala 20:22] + wire sd_auto_in_ar_ready; // @[SimMMIO.scala 20:22] + wire sd_auto_in_ar_valid; // @[SimMMIO.scala 20:22] + wire [1:0] sd_auto_in_ar_bits_id; // @[SimMMIO.scala 20:22] + wire [30:0] sd_auto_in_ar_bits_addr; // @[SimMMIO.scala 20:22] + wire [7:0] sd_auto_in_ar_bits_len; // @[SimMMIO.scala 20:22] + wire [2:0] sd_auto_in_ar_bits_size; // @[SimMMIO.scala 20:22] + wire [1:0] sd_auto_in_ar_bits_burst; // @[SimMMIO.scala 20:22] + wire sd_auto_in_ar_bits_lock; // @[SimMMIO.scala 20:22] + wire [3:0] sd_auto_in_ar_bits_cache; // @[SimMMIO.scala 20:22] + wire [2:0] sd_auto_in_ar_bits_prot; // @[SimMMIO.scala 20:22] + wire [3:0] sd_auto_in_ar_bits_qos; // @[SimMMIO.scala 20:22] + wire sd_auto_in_r_ready; // @[SimMMIO.scala 20:22] + wire sd_auto_in_r_valid; // @[SimMMIO.scala 20:22] + wire [1:0] sd_auto_in_r_bits_id; // @[SimMMIO.scala 20:22] + wire [63:0] sd_auto_in_r_bits_data; // @[SimMMIO.scala 20:22] + wire [1:0] sd_auto_in_r_bits_resp; // @[SimMMIO.scala 20:22] + wire sd_auto_in_r_bits_last; // @[SimMMIO.scala 20:22] + wire intrGen_clock; // @[SimMMIO.scala 21:27] + wire intrGen_reset; // @[SimMMIO.scala 21:27] + wire intrGen_auto_in_aw_ready; // @[SimMMIO.scala 21:27] + wire intrGen_auto_in_aw_valid; // @[SimMMIO.scala 21:27] + wire [1:0] intrGen_auto_in_aw_bits_id; // @[SimMMIO.scala 21:27] + wire [30:0] intrGen_auto_in_aw_bits_addr; // @[SimMMIO.scala 21:27] + wire [7:0] intrGen_auto_in_aw_bits_len; // @[SimMMIO.scala 21:27] + wire [2:0] intrGen_auto_in_aw_bits_size; // @[SimMMIO.scala 21:27] + wire [1:0] intrGen_auto_in_aw_bits_burst; // @[SimMMIO.scala 21:27] + wire intrGen_auto_in_aw_bits_lock; // @[SimMMIO.scala 21:27] + wire [3:0] intrGen_auto_in_aw_bits_cache; // @[SimMMIO.scala 21:27] + wire [2:0] intrGen_auto_in_aw_bits_prot; // @[SimMMIO.scala 21:27] + wire [3:0] intrGen_auto_in_aw_bits_qos; // @[SimMMIO.scala 21:27] + wire intrGen_auto_in_w_ready; // @[SimMMIO.scala 21:27] + wire intrGen_auto_in_w_valid; // @[SimMMIO.scala 21:27] + wire [63:0] intrGen_auto_in_w_bits_data; // @[SimMMIO.scala 21:27] + wire [7:0] intrGen_auto_in_w_bits_strb; // @[SimMMIO.scala 21:27] + wire intrGen_auto_in_w_bits_last; // @[SimMMIO.scala 21:27] + wire intrGen_auto_in_b_ready; // @[SimMMIO.scala 21:27] + wire intrGen_auto_in_b_valid; // @[SimMMIO.scala 21:27] + wire [1:0] intrGen_auto_in_b_bits_id; // @[SimMMIO.scala 21:27] + wire [1:0] intrGen_auto_in_b_bits_resp; // @[SimMMIO.scala 21:27] + wire intrGen_auto_in_ar_ready; // @[SimMMIO.scala 21:27] + wire intrGen_auto_in_ar_valid; // @[SimMMIO.scala 21:27] + wire [1:0] intrGen_auto_in_ar_bits_id; // @[SimMMIO.scala 21:27] + wire [30:0] intrGen_auto_in_ar_bits_addr; // @[SimMMIO.scala 21:27] + wire [7:0] intrGen_auto_in_ar_bits_len; // @[SimMMIO.scala 21:27] + wire [2:0] intrGen_auto_in_ar_bits_size; // @[SimMMIO.scala 21:27] + wire [1:0] intrGen_auto_in_ar_bits_burst; // @[SimMMIO.scala 21:27] + wire intrGen_auto_in_ar_bits_lock; // @[SimMMIO.scala 21:27] + wire [3:0] intrGen_auto_in_ar_bits_cache; // @[SimMMIO.scala 21:27] + wire [2:0] intrGen_auto_in_ar_bits_prot; // @[SimMMIO.scala 21:27] + wire [3:0] intrGen_auto_in_ar_bits_qos; // @[SimMMIO.scala 21:27] + wire intrGen_auto_in_r_ready; // @[SimMMIO.scala 21:27] + wire intrGen_auto_in_r_valid; // @[SimMMIO.scala 21:27] + wire [1:0] intrGen_auto_in_r_bits_id; // @[SimMMIO.scala 21:27] + wire [63:0] intrGen_auto_in_r_bits_data; // @[SimMMIO.scala 21:27] + wire [1:0] intrGen_auto_in_r_bits_resp; // @[SimMMIO.scala 21:27] + wire intrGen_auto_in_r_bits_last; // @[SimMMIO.scala 21:27] + wire [255:0] intrGen_io_extra_intrVec; // @[SimMMIO.scala 21:27] wire axi4xbar_clock; // @[Xbar.scala 218:30] wire axi4xbar_reset; // @[Xbar.scala 218:30] wire axi4xbar_auto_in_aw_ready; // @[Xbar.scala 218:30] @@ -274,6 +315,43 @@ module SimMMIO( wire [63:0] axi4xbar_auto_in_r_bits_data; // @[Xbar.scala 218:30] wire [1:0] axi4xbar_auto_in_r_bits_resp; // @[Xbar.scala 218:30] wire axi4xbar_auto_in_r_bits_last; // @[Xbar.scala 218:30] + wire axi4xbar_auto_out_5_aw_ready; // @[Xbar.scala 218:30] + wire axi4xbar_auto_out_5_aw_valid; // @[Xbar.scala 218:30] + wire [1:0] axi4xbar_auto_out_5_aw_bits_id; // @[Xbar.scala 218:30] + wire [30:0] axi4xbar_auto_out_5_aw_bits_addr; // @[Xbar.scala 218:30] + wire [7:0] axi4xbar_auto_out_5_aw_bits_len; // @[Xbar.scala 218:30] + wire [2:0] axi4xbar_auto_out_5_aw_bits_size; // @[Xbar.scala 218:30] + wire [1:0] axi4xbar_auto_out_5_aw_bits_burst; // @[Xbar.scala 218:30] + wire axi4xbar_auto_out_5_aw_bits_lock; // @[Xbar.scala 218:30] + wire [3:0] axi4xbar_auto_out_5_aw_bits_cache; // @[Xbar.scala 218:30] + wire [2:0] axi4xbar_auto_out_5_aw_bits_prot; // @[Xbar.scala 218:30] + wire [3:0] axi4xbar_auto_out_5_aw_bits_qos; // @[Xbar.scala 218:30] + wire axi4xbar_auto_out_5_w_ready; // @[Xbar.scala 218:30] + wire axi4xbar_auto_out_5_w_valid; // @[Xbar.scala 218:30] + wire [63:0] axi4xbar_auto_out_5_w_bits_data; // @[Xbar.scala 218:30] + wire [7:0] axi4xbar_auto_out_5_w_bits_strb; // @[Xbar.scala 218:30] + wire axi4xbar_auto_out_5_w_bits_last; // @[Xbar.scala 218:30] + wire axi4xbar_auto_out_5_b_ready; // @[Xbar.scala 218:30] + wire axi4xbar_auto_out_5_b_valid; // @[Xbar.scala 218:30] + wire [1:0] axi4xbar_auto_out_5_b_bits_id; // @[Xbar.scala 218:30] + wire [1:0] axi4xbar_auto_out_5_b_bits_resp; // @[Xbar.scala 218:30] + wire axi4xbar_auto_out_5_ar_ready; // @[Xbar.scala 218:30] + wire axi4xbar_auto_out_5_ar_valid; // @[Xbar.scala 218:30] + wire [1:0] axi4xbar_auto_out_5_ar_bits_id; // @[Xbar.scala 218:30] + wire [30:0] axi4xbar_auto_out_5_ar_bits_addr; // @[Xbar.scala 218:30] + wire [7:0] axi4xbar_auto_out_5_ar_bits_len; // @[Xbar.scala 218:30] + wire [2:0] axi4xbar_auto_out_5_ar_bits_size; // @[Xbar.scala 218:30] + wire [1:0] axi4xbar_auto_out_5_ar_bits_burst; // @[Xbar.scala 218:30] + wire axi4xbar_auto_out_5_ar_bits_lock; // @[Xbar.scala 218:30] + wire [3:0] axi4xbar_auto_out_5_ar_bits_cache; // @[Xbar.scala 218:30] + wire [2:0] axi4xbar_auto_out_5_ar_bits_prot; // @[Xbar.scala 218:30] + wire [3:0] axi4xbar_auto_out_5_ar_bits_qos; // @[Xbar.scala 218:30] + wire axi4xbar_auto_out_5_r_ready; // @[Xbar.scala 218:30] + wire axi4xbar_auto_out_5_r_valid; // @[Xbar.scala 218:30] + wire [1:0] axi4xbar_auto_out_5_r_bits_id; // @[Xbar.scala 218:30] + wire [63:0] axi4xbar_auto_out_5_r_bits_data; // @[Xbar.scala 218:30] + wire [1:0] axi4xbar_auto_out_5_r_bits_resp; // @[Xbar.scala 218:30] + wire axi4xbar_auto_out_5_r_bits_last; // @[Xbar.scala 218:30] wire axi4xbar_auto_out_4_aw_ready; // @[Xbar.scala 218:30] wire axi4xbar_auto_out_4_aw_valid; // @[Xbar.scala 218:30] wire [1:0] axi4xbar_auto_out_4_aw_bits_id; // @[Xbar.scala 218:30] @@ -454,7 +532,7 @@ module SimMMIO( wire [63:0] axi4xbar_auto_out_0_r_bits_data; // @[Xbar.scala 218:30] wire [1:0] axi4xbar_auto_out_0_r_bits_resp; // @[Xbar.scala 218:30] wire axi4xbar_auto_out_0_r_bits_last; // @[Xbar.scala 218:30] - AXI4Flash flash ( // @[SimMMIO.scala 11:25] + AXI4Flash flash ( // @[SimMMIO.scala 13:25] .clock(flash_clock), .reset(flash_reset), .auto_in_aw_ready(flash_auto_in_aw_ready), @@ -495,7 +573,7 @@ module SimMMIO( .auto_in_r_bits_resp(flash_auto_in_r_bits_resp), .auto_in_r_bits_last(flash_auto_in_r_bits_last) ); - AXI4UART uart ( // @[SimMMIO.scala 12:24] + AXI4UART uart ( // @[SimMMIO.scala 14:24] .clock(uart_clock), .reset(uart_reset), .auto_in_aw_ready(uart_auto_in_aw_ready), @@ -540,7 +618,7 @@ module SimMMIO( .io_extra_in_valid(uart_io_extra_in_valid), .io_extra_in_ch(uart_io_extra_in_ch) ); - AXI4VGA vga ( // @[SimMMIO.scala 13:23] + AXI4VGA vga ( // @[SimMMIO.scala 15:23] .clock(vga_clock), .reset(vga_reset), .auto_in_1_aw_ready(vga_auto_in_1_aw_ready), @@ -613,7 +691,7 @@ module SimMMIO( .auto_in_0_r_bits_id(vga_auto_in_0_r_bits_id), .auto_in_0_r_bits_last(vga_auto_in_0_r_bits_last) ); - AXI4DummySD sd ( // @[SimMMIO.scala 18:22] + AXI4DummySD sd ( // @[SimMMIO.scala 20:22] .clock(sd_clock), .reset(sd_reset), .auto_in_aw_ready(sd_auto_in_aw_ready), @@ -654,7 +732,49 @@ module SimMMIO( .auto_in_r_bits_resp(sd_auto_in_r_bits_resp), .auto_in_r_bits_last(sd_auto_in_r_bits_last) ); - AXI4Xbar_1 axi4xbar ( // @[Xbar.scala 218:30] + AXI4IntrGenerator intrGen ( // @[SimMMIO.scala 21:27] + .clock(intrGen_clock), + .reset(intrGen_reset), + .auto_in_aw_ready(intrGen_auto_in_aw_ready), + .auto_in_aw_valid(intrGen_auto_in_aw_valid), + .auto_in_aw_bits_id(intrGen_auto_in_aw_bits_id), + .auto_in_aw_bits_addr(intrGen_auto_in_aw_bits_addr), + .auto_in_aw_bits_len(intrGen_auto_in_aw_bits_len), + .auto_in_aw_bits_size(intrGen_auto_in_aw_bits_size), + .auto_in_aw_bits_burst(intrGen_auto_in_aw_bits_burst), + .auto_in_aw_bits_lock(intrGen_auto_in_aw_bits_lock), + .auto_in_aw_bits_cache(intrGen_auto_in_aw_bits_cache), + .auto_in_aw_bits_prot(intrGen_auto_in_aw_bits_prot), + .auto_in_aw_bits_qos(intrGen_auto_in_aw_bits_qos), + .auto_in_w_ready(intrGen_auto_in_w_ready), + .auto_in_w_valid(intrGen_auto_in_w_valid), + .auto_in_w_bits_data(intrGen_auto_in_w_bits_data), + .auto_in_w_bits_strb(intrGen_auto_in_w_bits_strb), + .auto_in_w_bits_last(intrGen_auto_in_w_bits_last), + .auto_in_b_ready(intrGen_auto_in_b_ready), + .auto_in_b_valid(intrGen_auto_in_b_valid), + .auto_in_b_bits_id(intrGen_auto_in_b_bits_id), + .auto_in_b_bits_resp(intrGen_auto_in_b_bits_resp), + .auto_in_ar_ready(intrGen_auto_in_ar_ready), + .auto_in_ar_valid(intrGen_auto_in_ar_valid), + .auto_in_ar_bits_id(intrGen_auto_in_ar_bits_id), + .auto_in_ar_bits_addr(intrGen_auto_in_ar_bits_addr), + .auto_in_ar_bits_len(intrGen_auto_in_ar_bits_len), + .auto_in_ar_bits_size(intrGen_auto_in_ar_bits_size), + .auto_in_ar_bits_burst(intrGen_auto_in_ar_bits_burst), + .auto_in_ar_bits_lock(intrGen_auto_in_ar_bits_lock), + .auto_in_ar_bits_cache(intrGen_auto_in_ar_bits_cache), + .auto_in_ar_bits_prot(intrGen_auto_in_ar_bits_prot), + .auto_in_ar_bits_qos(intrGen_auto_in_ar_bits_qos), + .auto_in_r_ready(intrGen_auto_in_r_ready), + .auto_in_r_valid(intrGen_auto_in_r_valid), + .auto_in_r_bits_id(intrGen_auto_in_r_bits_id), + .auto_in_r_bits_data(intrGen_auto_in_r_bits_data), + .auto_in_r_bits_resp(intrGen_auto_in_r_bits_resp), + .auto_in_r_bits_last(intrGen_auto_in_r_bits_last), + .io_extra_intrVec(intrGen_io_extra_intrVec) + ); + AXI4Xbar axi4xbar ( // @[Xbar.scala 218:30] .clock(axi4xbar_clock), .reset(axi4xbar_reset), .auto_in_aw_ready(axi4xbar_auto_in_aw_ready), @@ -694,6 +814,43 @@ module SimMMIO( .auto_in_r_bits_data(axi4xbar_auto_in_r_bits_data), .auto_in_r_bits_resp(axi4xbar_auto_in_r_bits_resp), .auto_in_r_bits_last(axi4xbar_auto_in_r_bits_last), + .auto_out_5_aw_ready(axi4xbar_auto_out_5_aw_ready), + .auto_out_5_aw_valid(axi4xbar_auto_out_5_aw_valid), + .auto_out_5_aw_bits_id(axi4xbar_auto_out_5_aw_bits_id), + .auto_out_5_aw_bits_addr(axi4xbar_auto_out_5_aw_bits_addr), + .auto_out_5_aw_bits_len(axi4xbar_auto_out_5_aw_bits_len), + .auto_out_5_aw_bits_size(axi4xbar_auto_out_5_aw_bits_size), + .auto_out_5_aw_bits_burst(axi4xbar_auto_out_5_aw_bits_burst), + .auto_out_5_aw_bits_lock(axi4xbar_auto_out_5_aw_bits_lock), + .auto_out_5_aw_bits_cache(axi4xbar_auto_out_5_aw_bits_cache), + .auto_out_5_aw_bits_prot(axi4xbar_auto_out_5_aw_bits_prot), + .auto_out_5_aw_bits_qos(axi4xbar_auto_out_5_aw_bits_qos), + .auto_out_5_w_ready(axi4xbar_auto_out_5_w_ready), + .auto_out_5_w_valid(axi4xbar_auto_out_5_w_valid), + .auto_out_5_w_bits_data(axi4xbar_auto_out_5_w_bits_data), + .auto_out_5_w_bits_strb(axi4xbar_auto_out_5_w_bits_strb), + .auto_out_5_w_bits_last(axi4xbar_auto_out_5_w_bits_last), + .auto_out_5_b_ready(axi4xbar_auto_out_5_b_ready), + .auto_out_5_b_valid(axi4xbar_auto_out_5_b_valid), + .auto_out_5_b_bits_id(axi4xbar_auto_out_5_b_bits_id), + .auto_out_5_b_bits_resp(axi4xbar_auto_out_5_b_bits_resp), + .auto_out_5_ar_ready(axi4xbar_auto_out_5_ar_ready), + .auto_out_5_ar_valid(axi4xbar_auto_out_5_ar_valid), + .auto_out_5_ar_bits_id(axi4xbar_auto_out_5_ar_bits_id), + .auto_out_5_ar_bits_addr(axi4xbar_auto_out_5_ar_bits_addr), + .auto_out_5_ar_bits_len(axi4xbar_auto_out_5_ar_bits_len), + .auto_out_5_ar_bits_size(axi4xbar_auto_out_5_ar_bits_size), + .auto_out_5_ar_bits_burst(axi4xbar_auto_out_5_ar_bits_burst), + .auto_out_5_ar_bits_lock(axi4xbar_auto_out_5_ar_bits_lock), + .auto_out_5_ar_bits_cache(axi4xbar_auto_out_5_ar_bits_cache), + .auto_out_5_ar_bits_prot(axi4xbar_auto_out_5_ar_bits_prot), + .auto_out_5_ar_bits_qos(axi4xbar_auto_out_5_ar_bits_qos), + .auto_out_5_r_ready(axi4xbar_auto_out_5_r_ready), + .auto_out_5_r_valid(axi4xbar_auto_out_5_r_valid), + .auto_out_5_r_bits_id(axi4xbar_auto_out_5_r_bits_id), + .auto_out_5_r_bits_data(axi4xbar_auto_out_5_r_bits_data), + .auto_out_5_r_bits_resp(axi4xbar_auto_out_5_r_bits_resp), + .auto_out_5_r_bits_last(axi4xbar_auto_out_5_r_bits_last), .auto_out_4_aw_ready(axi4xbar_auto_out_4_aw_ready), .auto_out_4_aw_valid(axi4xbar_auto_out_4_aw_valid), .auto_out_4_aw_bits_id(axi4xbar_auto_out_4_aw_bits_id), @@ -875,20 +1032,21 @@ module SimMMIO( .auto_out_0_r_bits_resp(axi4xbar_auto_out_0_r_bits_resp), .auto_out_0_r_bits_last(axi4xbar_auto_out_0_r_bits_last) ); - assign auto_axi4xbar_in_aw_ready = axi4xbar_auto_in_aw_ready; // @[LazyModule.scala 309:16] - assign auto_axi4xbar_in_w_ready = axi4xbar_auto_in_w_ready; // @[LazyModule.scala 309:16] - assign auto_axi4xbar_in_b_valid = axi4xbar_auto_in_b_valid; // @[LazyModule.scala 309:16] - assign auto_axi4xbar_in_b_bits_id = axi4xbar_auto_in_b_bits_id; // @[LazyModule.scala 309:16] - assign auto_axi4xbar_in_b_bits_resp = axi4xbar_auto_in_b_bits_resp; // @[LazyModule.scala 309:16] - assign auto_axi4xbar_in_ar_ready = axi4xbar_auto_in_ar_ready; // @[LazyModule.scala 309:16] - assign auto_axi4xbar_in_r_valid = axi4xbar_auto_in_r_valid; // @[LazyModule.scala 309:16] - assign auto_axi4xbar_in_r_bits_id = axi4xbar_auto_in_r_bits_id; // @[LazyModule.scala 309:16] - assign auto_axi4xbar_in_r_bits_data = axi4xbar_auto_in_r_bits_data; // @[LazyModule.scala 309:16] - assign auto_axi4xbar_in_r_bits_resp = axi4xbar_auto_in_r_bits_resp; // @[LazyModule.scala 309:16] - assign auto_axi4xbar_in_r_bits_last = axi4xbar_auto_in_r_bits_last; // @[LazyModule.scala 309:16] - assign io_uart_out_valid = uart_io_extra_out_valid; // @[SimMMIO.scala 31:13] - assign io_uart_out_ch = uart_io_extra_out_ch; // @[SimMMIO.scala 31:13] - assign io_uart_in_valid = uart_io_extra_in_valid; // @[SimMMIO.scala 31:13] + assign io_axi4_0_aw_ready = axi4xbar_auto_in_aw_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16] + assign io_axi4_0_w_ready = axi4xbar_auto_in_w_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16] + assign io_axi4_0_b_valid = axi4xbar_auto_in_b_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16] + assign io_axi4_0_b_bits_id = axi4xbar_auto_in_b_bits_id; // @[Nodes.scala 1207:84 LazyModule.scala 298:16] + assign io_axi4_0_b_bits_resp = axi4xbar_auto_in_b_bits_resp; // @[Nodes.scala 1207:84 LazyModule.scala 298:16] + assign io_axi4_0_ar_ready = axi4xbar_auto_in_ar_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16] + assign io_axi4_0_r_valid = axi4xbar_auto_in_r_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16] + assign io_axi4_0_r_bits_id = axi4xbar_auto_in_r_bits_id; // @[Nodes.scala 1207:84 LazyModule.scala 298:16] + assign io_axi4_0_r_bits_data = axi4xbar_auto_in_r_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16] + assign io_axi4_0_r_bits_resp = axi4xbar_auto_in_r_bits_resp; // @[Nodes.scala 1207:84 LazyModule.scala 298:16] + assign io_axi4_0_r_bits_last = axi4xbar_auto_in_r_bits_last; // @[Nodes.scala 1207:84 LazyModule.scala 298:16] + assign io_uart_out_valid = uart_io_extra_out_valid; // @[SimMMIO.scala 46:13] + assign io_uart_out_ch = uart_io_extra_out_ch; // @[SimMMIO.scala 46:13] + assign io_uart_in_valid = uart_io_extra_in_valid; // @[SimMMIO.scala 46:13] + assign io_interrupt_intrVec = intrGen_io_extra_intrVec; // @[SimMMIO.scala 47:18] assign flash_clock = clock; assign flash_reset = reset; assign flash_auto_in_aw_valid = axi4xbar_auto_out_3_aw_valid; // @[LazyModule.scala 296:16] @@ -945,7 +1103,7 @@ module SimMMIO( assign uart_auto_in_ar_bits_prot = axi4xbar_auto_out_0_ar_bits_prot; // @[LazyModule.scala 296:16] assign uart_auto_in_ar_bits_qos = axi4xbar_auto_out_0_ar_bits_qos; // @[LazyModule.scala 296:16] assign uart_auto_in_r_ready = axi4xbar_auto_out_0_r_ready; // @[LazyModule.scala 296:16] - assign uart_io_extra_in_ch = io_uart_in_ch; // @[SimMMIO.scala 31:13] + assign uart_io_extra_in_ch = io_uart_in_ch; // @[SimMMIO.scala 46:13] assign vga_clock = clock; assign vga_reset = reset; assign vga_auto_in_1_aw_valid = axi4xbar_auto_out_2_aw_valid; // @[LazyModule.scala 296:16] @@ -1026,34 +1184,73 @@ module SimMMIO( assign sd_auto_in_ar_bits_prot = axi4xbar_auto_out_4_ar_bits_prot; // @[LazyModule.scala 296:16] assign sd_auto_in_ar_bits_qos = axi4xbar_auto_out_4_ar_bits_qos; // @[LazyModule.scala 296:16] assign sd_auto_in_r_ready = axi4xbar_auto_out_4_r_ready; // @[LazyModule.scala 296:16] + assign intrGen_clock = clock; + assign intrGen_reset = reset; + assign intrGen_auto_in_aw_valid = axi4xbar_auto_out_5_aw_valid; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_aw_bits_id = axi4xbar_auto_out_5_aw_bits_id; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_aw_bits_addr = axi4xbar_auto_out_5_aw_bits_addr; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_aw_bits_len = axi4xbar_auto_out_5_aw_bits_len; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_aw_bits_size = axi4xbar_auto_out_5_aw_bits_size; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_aw_bits_burst = axi4xbar_auto_out_5_aw_bits_burst; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_aw_bits_lock = axi4xbar_auto_out_5_aw_bits_lock; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_aw_bits_cache = axi4xbar_auto_out_5_aw_bits_cache; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_aw_bits_prot = axi4xbar_auto_out_5_aw_bits_prot; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_aw_bits_qos = axi4xbar_auto_out_5_aw_bits_qos; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_w_valid = axi4xbar_auto_out_5_w_valid; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_w_bits_data = axi4xbar_auto_out_5_w_bits_data; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_w_bits_strb = axi4xbar_auto_out_5_w_bits_strb; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_w_bits_last = axi4xbar_auto_out_5_w_bits_last; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_b_ready = axi4xbar_auto_out_5_b_ready; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_ar_valid = axi4xbar_auto_out_5_ar_valid; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_ar_bits_id = axi4xbar_auto_out_5_ar_bits_id; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_ar_bits_addr = axi4xbar_auto_out_5_ar_bits_addr; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_ar_bits_len = axi4xbar_auto_out_5_ar_bits_len; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_ar_bits_size = axi4xbar_auto_out_5_ar_bits_size; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_ar_bits_burst = axi4xbar_auto_out_5_ar_bits_burst; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_ar_bits_lock = axi4xbar_auto_out_5_ar_bits_lock; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_ar_bits_cache = axi4xbar_auto_out_5_ar_bits_cache; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_ar_bits_prot = axi4xbar_auto_out_5_ar_bits_prot; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_ar_bits_qos = axi4xbar_auto_out_5_ar_bits_qos; // @[LazyModule.scala 296:16] + assign intrGen_auto_in_r_ready = axi4xbar_auto_out_5_r_ready; // @[LazyModule.scala 296:16] assign axi4xbar_clock = clock; assign axi4xbar_reset = reset; - assign axi4xbar_auto_in_aw_valid = auto_axi4xbar_in_aw_valid; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_aw_bits_id = auto_axi4xbar_in_aw_bits_id; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_aw_bits_addr = auto_axi4xbar_in_aw_bits_addr; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_aw_bits_len = auto_axi4xbar_in_aw_bits_len; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_aw_bits_size = auto_axi4xbar_in_aw_bits_size; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_aw_bits_burst = auto_axi4xbar_in_aw_bits_burst; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_aw_bits_lock = auto_axi4xbar_in_aw_bits_lock; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_aw_bits_cache = auto_axi4xbar_in_aw_bits_cache; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_aw_bits_prot = auto_axi4xbar_in_aw_bits_prot; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_aw_bits_qos = auto_axi4xbar_in_aw_bits_qos; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_w_valid = auto_axi4xbar_in_w_valid; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_w_bits_data = auto_axi4xbar_in_w_bits_data; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_w_bits_strb = auto_axi4xbar_in_w_bits_strb; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_w_bits_last = auto_axi4xbar_in_w_bits_last; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_b_ready = auto_axi4xbar_in_b_ready; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_ar_valid = auto_axi4xbar_in_ar_valid; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_ar_bits_id = auto_axi4xbar_in_ar_bits_id; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_ar_bits_addr = auto_axi4xbar_in_ar_bits_addr; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_ar_bits_len = auto_axi4xbar_in_ar_bits_len; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_ar_bits_size = auto_axi4xbar_in_ar_bits_size; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_ar_bits_burst = auto_axi4xbar_in_ar_bits_burst; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_ar_bits_lock = auto_axi4xbar_in_ar_bits_lock; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_ar_bits_cache = auto_axi4xbar_in_ar_bits_cache; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_ar_bits_prot = auto_axi4xbar_in_ar_bits_prot; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_ar_bits_qos = auto_axi4xbar_in_ar_bits_qos; // @[LazyModule.scala 309:16] - assign axi4xbar_auto_in_r_ready = auto_axi4xbar_in_r_ready; // @[LazyModule.scala 309:16] + assign axi4xbar_auto_in_aw_valid = io_axi4_0_aw_valid; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_aw_bits_id = io_axi4_0_aw_bits_id; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_aw_bits_addr = io_axi4_0_aw_bits_addr; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_aw_bits_len = io_axi4_0_aw_bits_len; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_aw_bits_size = io_axi4_0_aw_bits_size; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_aw_bits_burst = io_axi4_0_aw_bits_burst; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_aw_bits_lock = io_axi4_0_aw_bits_lock; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_aw_bits_cache = io_axi4_0_aw_bits_cache; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_aw_bits_prot = io_axi4_0_aw_bits_prot; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_aw_bits_qos = io_axi4_0_aw_bits_qos; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_w_valid = io_axi4_0_w_valid; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_w_bits_data = io_axi4_0_w_bits_data; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_w_bits_strb = io_axi4_0_w_bits_strb; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_w_bits_last = io_axi4_0_w_bits_last; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_b_ready = io_axi4_0_b_ready; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_ar_valid = io_axi4_0_ar_valid; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_ar_bits_id = io_axi4_0_ar_bits_id; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_ar_bits_addr = io_axi4_0_ar_bits_addr; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_ar_bits_len = io_axi4_0_ar_bits_len; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_ar_bits_size = io_axi4_0_ar_bits_size; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_ar_bits_burst = io_axi4_0_ar_bits_burst; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_ar_bits_lock = io_axi4_0_ar_bits_lock; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_ar_bits_cache = io_axi4_0_ar_bits_cache; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_ar_bits_prot = io_axi4_0_ar_bits_prot; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_ar_bits_qos = io_axi4_0_ar_bits_qos; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_in_r_ready = io_axi4_0_r_ready; // @[Nodes.scala 1207:84 Nodes.scala 1630:60] + assign axi4xbar_auto_out_5_aw_ready = intrGen_auto_in_aw_ready; // @[LazyModule.scala 296:16] + assign axi4xbar_auto_out_5_w_ready = intrGen_auto_in_w_ready; // @[LazyModule.scala 296:16] + assign axi4xbar_auto_out_5_b_valid = intrGen_auto_in_b_valid; // @[LazyModule.scala 296:16] + assign axi4xbar_auto_out_5_b_bits_id = intrGen_auto_in_b_bits_id; // @[LazyModule.scala 296:16] + assign axi4xbar_auto_out_5_b_bits_resp = intrGen_auto_in_b_bits_resp; // @[LazyModule.scala 296:16] + assign axi4xbar_auto_out_5_ar_ready = intrGen_auto_in_ar_ready; // @[LazyModule.scala 296:16] + assign axi4xbar_auto_out_5_r_valid = intrGen_auto_in_r_valid; // @[LazyModule.scala 296:16] + assign axi4xbar_auto_out_5_r_bits_id = intrGen_auto_in_r_bits_id; // @[LazyModule.scala 296:16] + assign axi4xbar_auto_out_5_r_bits_data = intrGen_auto_in_r_bits_data; // @[LazyModule.scala 296:16] + assign axi4xbar_auto_out_5_r_bits_resp = intrGen_auto_in_r_bits_resp; // @[LazyModule.scala 296:16] + assign axi4xbar_auto_out_5_r_bits_last = intrGen_auto_in_r_bits_last; // @[LazyModule.scala 296:16] assign axi4xbar_auto_out_4_aw_ready = sd_auto_in_aw_ready; // @[LazyModule.scala 296:16] assign axi4xbar_auto_out_4_w_ready = sd_auto_in_w_ready; // @[LazyModule.scala 296:16] assign axi4xbar_auto_out_4_b_valid = sd_auto_in_b_valid; // @[LazyModule.scala 296:16] @@ -1107,3 +1304,4 @@ module SimMMIO( assign axi4xbar_auto_out_0_r_bits_resp = uart_auto_in_r_bits_resp; // @[LazyModule.scala 296:16] assign axi4xbar_auto_out_0_r_bits_last = uart_auto_in_r_bits_last; // @[LazyModule.scala 296:16] endmodule + diff --git a/vcs/testbench/SimMMIO/VGACtrl.v b/vcs/testbench/SimMMIO/VGACtrl.v index 5cd307b..fdf7973 100644 --- a/vcs/testbench/SimMMIO/VGACtrl.v +++ b/vcs/testbench/SimMMIO/VGACtrl.v @@ -47,22 +47,22 @@ module VGACtrl( reg [31:0] _RAND_4; reg [31:0] _RAND_5; `endif // RANDOMIZE_REG_INIT - reg [1:0] state; // @[AXI4SlaveModule.scala 80:22] - wire _T_61 = state == 2'h0; // @[AXI4SlaveModule.scala 138:24] - wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 138:24] + reg [1:0] state; // @[AXI4SlaveModule.scala 79:22] + wire _T_61 = state == 2'h0; // @[AXI4SlaveModule.scala 137:24] + wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 137:24] wire in_ar_valid = auto_in_ar_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T = in_ar_ready & in_ar_valid; // @[Decoupled.scala 40:37] - wire in_aw_ready = _T_61 & ~in_ar_valid; // @[AXI4SlaveModule.scala 156:35] + wire in_aw_ready = _T_61 & ~in_ar_valid; // @[AXI4SlaveModule.scala 155:35] wire in_aw_valid = auto_in_aw_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T_1 = in_aw_ready & in_aw_valid; // @[Decoupled.scala 40:37] - wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 157:23] + wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 156:23] wire in_w_valid = auto_in_w_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire _T_2 = in_w_ready & in_w_valid; // @[Decoupled.scala 40:37] wire in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 160:22] + wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 159:22] wire _T_3 = in_b_ready & in_b_valid; // @[Decoupled.scala 40:37] wire in_r_ready = auto_in_r_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 140:23] + wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 139:23] wire _T_4 = in_r_ready & in_r_valid; // @[Decoupled.scala 40:37] wire [1:0] in_aw_bits_burst = auto_in_aw_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [1:0] in_ar_bits_burst = auto_in_ar_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -72,26 +72,26 @@ module VGACtrl( wire [7:0] in_ar_bits_len = auto_in_ar_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [7:0] r; // @[Reg.scala 27:20] wire [7:0] _T_43 = _T ? in_ar_bits_len : r; // @[Hold.scala 7:48] - wire in_r_bits_last = value == _T_43; // @[AXI4SlaveModule.scala 118:32] + wire in_r_bits_last = value == _T_43; // @[AXI4SlaveModule.scala 117:32] wire _T_21 = 2'h2 == state; // @[Conditional.scala 37:30] wire in_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 97:42 AXI4SlaveModule.scala 98:15 AXI4SlaveModule.scala 80:22] + wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 96:42 AXI4SlaveModule.scala 97:15 AXI4SlaveModule.scala 79:22] wire _T_24 = 2'h3 == state; // @[Conditional.scala 37:30] - wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 102:24 AXI4SlaveModule.scala 103:15 AXI4SlaveModule.scala 80:22] - wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 80:22] + wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 101:24 AXI4SlaveModule.scala 102:15 AXI4SlaveModule.scala 79:22] + wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 79:22] wire [7:0] in_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [30:0] r_1; // @[Reg.scala 27:20] wire [30:0] in_ar_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [30:0] _GEN_10 = _T ? in_ar_bits_addr : r_1; // @[Reg.scala 28:19 Reg.scala 28:23 Reg.scala 27:20] wire [7:0] _value_T_1 = value + 8'h1; // @[Counter.scala 76:24] - wire _T_50 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 129:26] - wire _T_51 = in_ar_bits_len == 8'h0 | _T_50; // @[AXI4SlaveModule.scala 128:32] - wire _T_52 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 130:26] - wire _T_53 = _T_51 | _T_52; // @[AXI4SlaveModule.scala 129:34] - wire _T_54 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 131:26] - wire _T_55 = _T_53 | _T_54; // @[AXI4SlaveModule.scala 130:34] - wire _T_56 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 132:26] - wire _T_57 = _T_55 | _T_56; // @[AXI4SlaveModule.scala 131:34] + wire _T_50 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 128:26] + wire _T_51 = in_ar_bits_len == 8'h0 | _T_50; // @[AXI4SlaveModule.scala 127:32] + wire _T_52 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 129:26] + wire _T_53 = _T_51 | _T_52; // @[AXI4SlaveModule.scala 128:34] + wire _T_54 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 130:26] + wire _T_55 = _T_53 | _T_54; // @[AXI4SlaveModule.scala 129:34] + wire _T_56 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 131:26] + wire _T_57 = _T_55 | _T_56; // @[AXI4SlaveModule.scala 130:34] wire [30:0] in_aw_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] reg [1:0] r_3; // @[Reg.scala 15:16] wire [1:0] in_aw_bits_id = auto_in_aw_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] @@ -110,16 +110,16 @@ module VGACtrl( wire [2:0] in_aw_bits_prot = auto_in_aw_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_aw_bits_qos = auto_in_aw_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [63:0] in_w_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 162:16] - wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 159:18] + wire [1:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 161:16] + wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 158:18] wire [2:0] in_ar_bits_size = auto_in_ar_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire in_ar_bits_lock = auto_in_ar_bits_lock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_ar_bits_cache = auto_in_ar_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [2:0] in_ar_bits_prot = auto_in_ar_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] wire [3:0] in_ar_bits_qos = auto_in_ar_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16] - wire [1:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 164:16] + wire [1:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 163:16] wire [63:0] in_r_bits_data = {{32'd0}, _T_99}; // @[Nodes.scala 1210:84 RegMap.scala 12:11] - wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 139:18] + wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 138:18] assign auto_in_aw_ready = in_aw_ready; // @[LazyModule.scala 309:16] assign auto_in_w_ready = in_w_ready; // @[LazyModule.scala 309:16] assign auto_in_b_valid = in_b_valid; // @[LazyModule.scala 309:16] @@ -132,17 +132,17 @@ module VGACtrl( assign auto_in_r_bits_resp = in_b_bits_resp; // @[LazyModule.scala 309:16] assign auto_in_r_bits_last = in_r_bits_last; // @[LazyModule.scala 309:16] always @(posedge clock) begin - if (reset) begin // @[AXI4SlaveModule.scala 80:22] - state <= 2'h0; // @[AXI4SlaveModule.scala 80:22] + if (reset) begin // @[AXI4SlaveModule.scala 79:22] + state <= 2'h0; // @[AXI4SlaveModule.scala 79:22] end else if (_T_15) begin // @[Conditional.scala 40:58] - if (_T_1) begin // @[AXI4SlaveModule.scala 87:25] - state <= 2'h2; // @[AXI4SlaveModule.scala 88:15] - end else if (_T) begin // @[AXI4SlaveModule.scala 84:25] - state <= 2'h1; // @[AXI4SlaveModule.scala 85:15] + if (_T_1) begin // @[AXI4SlaveModule.scala 86:25] + state <= 2'h2; // @[AXI4SlaveModule.scala 87:15] + end else if (_T) begin // @[AXI4SlaveModule.scala 83:25] + state <= 2'h1; // @[AXI4SlaveModule.scala 84:15] end end else if (_T_18) begin // @[Conditional.scala 39:67] - if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 92:42] - state <= 2'h0; // @[AXI4SlaveModule.scala 93:15] + if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 91:42] + state <= 2'h0; // @[AXI4SlaveModule.scala 92:15] end end else if (_T_21) begin // @[Conditional.scala 39:67] state <= _GEN_3; @@ -151,9 +151,9 @@ module VGACtrl( end if (reset) begin // @[Counter.scala 60:40] value <= 8'h0; // @[Counter.scala 60:40] - end else if (_T_4) begin // @[AXI4SlaveModule.scala 120:23] - if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 122:28] - value <= 8'h0; // @[AXI4SlaveModule.scala 123:17] + end else if (_T_4) begin // @[AXI4SlaveModule.scala 119:23] + if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 121:28] + value <= 8'h0; // @[AXI4SlaveModule.scala 122:17] end else begin value <= _value_T_1; // @[Counter.scala 76:15] end @@ -180,70 +180,37 @@ module VGACtrl( `endif if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin $fwrite(32'h80000002, - "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:72 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" - ); // @[AXI4SlaveModule.scala 72:11] + "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:71 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" + ); // @[AXI4SlaveModule.scala 71:11] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 72:11] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin $fwrite(32'h80000002, - "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:75 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" - ); // @[AXI4SlaveModule.scala 75:11] + "Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:74 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n" + ); // @[AXI4SlaveModule.scala 74:11] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 75:11] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS - `ifndef SYNTHESIS `ifdef PRINTF_COND if (`PRINTF_COND) begin `endif if (_T & ~(_T_57 | reset)) begin - $fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:127 assert(\n"); // @[AXI4SlaveModule.scala 127:13] + $fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:126 assert(\n"); // @[AXI4SlaveModule.scala 126:13] end `ifdef PRINTF_COND end `endif `endif // SYNTHESIS - `ifndef SYNTHESIS - `ifdef STOP_COND - if (`STOP_COND) begin - `endif - if (_T & ~(_T_57 | reset)) begin - $fatal; // @[AXI4SlaveModule.scala 127:13] - end - `ifdef STOP_COND - end - `endif - `endif // SYNTHESIS end // Register and memory initialization `ifdef RANDOMIZE_GARBAGE_ASSIGN @@ -301,3 +268,4 @@ end // initial `endif `endif // SYNTHESIS endmodule + diff --git a/vcs/testbench/common.h b/vcs/testbench/common.h new file mode 100644 index 0000000..589f610 --- /dev/null +++ b/vcs/testbench/common.h @@ -0,0 +1,31 @@ +#ifndef __COMMON_H +#define __COMMON_H + +#include +#include +#include +#include +#include +#include + +#ifndef EMU_CORES +#define EMU_CORES 1 +#endif + +#define ANSI_COLOR_RED "\x1b[31m" +#define ANSI_COLOR_GREEN "\x1b[32m" +#define ANSI_COLOR_YELLOW "\x1b[33m" +#define ANSI_COLOR_BLUE "\x1b[34m" +#define ANSI_COLOR_MAGENTA "\x1b[35m" +#define ANSI_COLOR_CYAN "\x1b[36m" +#define ANSI_COLOR_RESET "\x1b[0m" + +#define eprintf(...) fprintf(stdout, ## __VA_ARGS__) + +typedef uint64_t rtlreg_t; +typedef uint64_t paddr_t; +typedef uint64_t vaddr_t; +typedef uint16_t ioaddr_t; + +#endif // __COMMON_H + diff --git a/vcs/testbench/flash.c b/vcs/testbench/flash.c new file mode 100644 index 0000000..736dbea --- /dev/null +++ b/vcs/testbench/flash.c @@ -0,0 +1,39 @@ +#include "common.h" + +// #define USE_BIN + +FILE *flash_fp = NULL; + +void flash_read(uint32_t addr, uint64_t *data) { +#ifdef USE_BIN + fseek(flash_fp, addr, SEEK_SET); + fread(data, 8, 1, flash_fp); +#else + uint32_t index = addr & 0x00000fff; + switch(index>>3){ + case 0 : + *data = 0x01f292930010029b; + break; + case 1 : + *data = 0x00028067; + break; + default : + *data = 0; + } +#endif +} + +void init_flash(void) { +#ifdef USE_BIN + + flash_fp = fopen("/home/jy/Project/nexus-am/tests/cputest/build/dummy-riscv64-noop.bin", "r"); + if(!flash_fp) + { + eprintf(ANSI_COLOR_MAGENTA "[warning] flash img not found\n"); + } + printf("use bin as a flash!\n"); +#else + printf("use fixed 3 instructions!\n"); +#endif +} + diff --git a/vcs/testbench/ram.c b/vcs/testbench/ram.c index 0c51630..bede468 100644 --- a/vcs/testbench/ram.c +++ b/vcs/testbench/ram.c @@ -1,8 +1,5 @@ +#include "common.h" #include -#include -#include -#include -#include #define EMU_RAM_SIZE (256 * 1024 * 1024UL) @@ -72,3 +69,4 @@ void ram_write_helper(uint64_t wIdx, uint64_t wdata, uint64_t wmask, uint8_t wen ram[wIdx] = (ram[wIdx] & ~wmask) | (wdata & wmask); } } + diff --git a/vcs/testbench/remove_x.py b/vcs/testbench/remove_x.py new file mode 100644 index 0000000..bce1a10 --- /dev/null +++ b/vcs/testbench/remove_x.py @@ -0,0 +1,170 @@ +import sys + +need_initial = [ + # not initialized registers (from rocket-chip and chisel lib) + # (1) RRArbiter.lastGrant; (2) PLRU replacement init state + ("`CORE.memBlock.dcache.missReqArb.lastGrant", 2), + ("`CORE.memBlock.dcache.missQueue.pipe_req_arb.lastGrant", 4), + ("`CORE.memBlock.dcache.storeReplayUnit.pipe_req_arb.lastGrant", 4), + ("`CORE.memBlock.dcache.storeReplayUnit.resp_arb.lastGrant", 4), + ("`CORE.memBlock.dcache.probeQueue.pipe_req_arb.lastGrant", 4), + ("`CORE.memBlock.dcache.mainPipeReqArb.lastGrant", 2), +] +for i in range(256): + need_initial.append((f"`CORE.l1pluscache.pipe.REG_1_{i}", 7)) +for i in range(64): + need_initial.append((f"`CORE.frontend.ifu.icache.REG_1_{i}", 3)) +for i in range(64): + need_initial.append((f"`CORE.memBlock.dcache.mainPipe.REG_4_{i}", 7)) +for i in range(64): + need_initial.append((f"`CORE.ptw.REG_19_{i}", 7)) + need_initial.append((f"`CORE.ptw.REG_38_{i}", 15)) + + +need_force = [ + # unknown reason (fetch x?) + ("`CORE.frontend.instrUncache.io_resp_bits_data", 256), + ("`CORE.frontend.instrUncache.entries_0.io_resp_bits_data", 256), + ("`CORE.frontend.ifu.io_redirect_bits_cfiUpdate_pc", 39),#X cause LOOP to be X + ("`CORE.frontend.ifu.io_redirect_bits_cfiUpdate_target", 39),#X cause LOOP to be X + # dual-port SRAMs read and write the same index at the same clock cycle + ("`CORE.frontend.ifu.bpu.bim.bim.array.array_2_ext.R0_data", 32), + ("`CORE.frontend.ifu.bpu.preds_3.tables_5.lo_us.array.array_3_ext.R0_data", 16), + ("`CORE.frontend.ifu.bpu.preds_3.tables_5.hi_us.array.array_3_ext.R0_data", 16), + ("`CORE.frontend.ifu.bpu.preds_3.tables_5.table_.array.array_7_ext.R0_data", 208), + ("`CORE.frontend.ifu.bpu.preds_3.tables_4.lo_us.array.array_3_ext.R0_data", 16), + ("`CORE.frontend.ifu.bpu.preds_3.tables_4.hi_us.array.array_3_ext.R0_data", 16), + ("`CORE.frontend.ifu.bpu.preds_3.tables_4.table_.array.array_7_ext.R0_data", 208), + ("`CORE.frontend.ifu.bpu.preds_3.tables_3.lo_us.array.array_5_ext.R0_data", 16), + ("`CORE.frontend.ifu.bpu.preds_3.tables_3.hi_us.array.array_5_ext.R0_data", 16), + ("`CORE.frontend.ifu.bpu.preds_3.tables_3.table_.array.array_6_ext.R0_data", 192), + ("`CORE.frontend.ifu.bpu.preds_3.tables_2.hi_us.array.array_5_ext.R0_data", 16), + ("`CORE.frontend.ifu.bpu.preds_3.tables_2.lo_us.array.array_5_ext.R0_data", 16), + ("`CORE.frontend.ifu.bpu.preds_3.tables_2.table_.array.array_6_ext.R0_data", 192), + ("`CORE.frontend.ifu.bpu.preds_3.tables_1.hi_us.array.array_3_ext.R0_data", 16), + ("`CORE.frontend.ifu.bpu.preds_3.tables_1.lo_us.array.array_3_ext.R0_data", 16), + ("`CORE.frontend.ifu.bpu.preds_3.tables_1.table_.array.array_4_ext.R0_data", 176), + ("`CORE.frontend.ifu.bpu.preds_3.tables_0.lo_us.array.array_3_ext.R0_data", 16), + ("`CORE.frontend.ifu.bpu.preds_3.tables_0.hi_us.array.array_3_ext.R0_data", 16), + ("`CORE.frontend.ifu.bpu.preds_3.tables_0.table_.array.array_4_ext.R0_data", 176), + ("`CORE.frontend.ifu.bpu.preds_3.scTables_5.table_.array.array_8_ext.R0_data", 192), + ("`CORE.frontend.ifu.bpu.preds_3.scTables_4.table_.array.array_8_ext.R0_data", 192), + ("`CORE.frontend.ifu.bpu.preds_3.scTables_3.table_.array.array_8_ext.R0_data", 192), + ("`CORE.frontend.ifu.bpu.preds_3.scTables_2.table_.array.array_8_ext.R0_data", 192), + ("`CORE.frontend.ifu.bpu.preds_3.scTables_1.table_.array.array_8_ext.R0_data", 192), + ("`CORE.frontend.ifu.bpu.preds_3.scTables_0.table_.array.array_8_ext.R0_data", 192), + ("`CORE.ctrlBlock.ftq.ftq_2r_sram.SRAMTemplate_1.array.array_19_ext.R0_data", 275), + ("`CORE.ctrlBlock.ftq.ftq_2r_sram.SRAMTemplate.array.array_19_ext.R0_data", 275), + ("`CORE.ctrlBlock.ftq.pred_target_sram.SRAMTemplate.array.array_20_ext.R0_data", 39), + #("`CORE.ctrlBlock.ftq.ftq_1r_sram.SRAMTemplate.array.array_21_ext.R0_data", 944), + ("`CORE.ctrlBlock.rename.FreeList_1.io_req_canAlloc", 1), + ("tb_top.sim.CPU.axi4deint.REG_1", 5), +] + +need_force_1 = [ + ("`CORE.ctrlBlock.ftq.ftq_1r_sram.SRAMTemplate.array.array_21_ext.R0_data", 944), + ("`CORE.frontend.ifu.icache.icacheMissQueue.io_resp_bits_data", 512), +] + +# QN +all_modules = [ + ("`CORE.l1pluscache.pipe.", "/home/xyn/debug/gate/vcs_newgate/20210530-gate/XSCore/L1plusCachePipe.v", "REG_1_"), + ("`CORE.frontend.ifu.icache.", "/home/xyn/debug/gate/vcs_newgate/20210530-gate/XSCore/ICache.v", "REG_1_"), + ("`CORE.memBlock.dcache.mainPipe.", "/home/xyn/debug/gate/vcs_newgate/20210530-gate/XSCore/DCache_MainPipe_0.v", "REG_4_"), + ("`CORE.ptw.", "/home/xyn/debug/gate/vcs_newgate/20210530-gate/XSCore/PTW.v", "REG_19_"), + ("`CORE.ptw.", "/home/xyn/debug/gate/vcs_newgate/20210530-gate/XSCore/PTW.v", "REG_38_"), +] + +def find_qn(level, filename, prefix): + all_qn = [] + last_line = "" + with open(filename) as f: + for line in f: + if ".QN(" in line: + cell_name = last_line.split()[1] + if cell_name.startswith(prefix): + all_qn.append(level + cell_name) + # if not cell_name.startswith("REG_"): + # all_remove = [" l3v", " l2v", " l3_", " l3g", " l1v", " l2_", "ppn_", " l1_", " l1g_", " sp_"] + # found = False + # for x in all_remove: + # if x in last_line or x in line: + # found = True + # continue + # if not found: + # print(last_line.strip() + line) + else: + last_line = line + return all_qn + +def rtl_generate(): + for source, width in need_initial: + assert(width < 64) + source_name = f"{source}" + print("initial begin") + print(f" force {source_name} = $random();") + print(f" #10 release {source_name};") + print("end") + + print("always @(clock) begin") + for source, width in need_force + need_force_1: + for i in range(width): + source_name = f"{source}" + if width > 1: + source_name += f"[{i}]" + print(f"if ({source_name} === 1'bx) begin") + print(f" force {source_name} = $random();") + print(f"end") + print(f"else begin release {source_name}; end") + print("end") + + +def netlist_generate(): + print("always @(clock) begin") + for source, width in need_force_1: + for i in range(width): + source_name = f"{source}_{i}_" + if "io_resp_bits_data" in source and i in [328, 135, 79]: + source_name += "_BAR" + print(f"if ({source_name} === 1'bx) begin") + print(f" force {source_name} = $random();") + print(f"end") + print(f"else begin release {source_name}; end") + + for source, width in need_initial: + for i in range(width): + source_name = f"{source}_reg_{i}_.Q" + print(f"if ({source_name} === 1'bx) begin") + print(f" force {source_name} = $random();") + print(f"end") + print(f"else begin release {source_name}; end") + + need_qn = [] + for level, module, prefix in all_modules: + need_qn += find_qn(level, module, prefix) + + for source in need_qn: + source_name = f"{source}.QN" + print(f"if ({source_name} === 1'bx) begin") + print(f" force {source_name} = $random();") + print(f"end") + print(f"else begin release {source_name}; end") + + for source, width in need_force: + for i in range(width): + source_name = f"{source}" + if width > 1: + source_name += f"[{i}]" + print(f"if ({source_name} === 1'bx) begin") + print(f" force {source_name} = $random();") + print(f"end") + print(f"else begin release {source_name}; end") + print("end") + +if __name__ == "__main__": + func_map = { + "rtl": rtl_generate, + "netlist": netlist_generate + } + func_map[sys.argv[1]]() + diff --git a/vcs/testbench/sim_top.v b/vcs/testbench/sim_top.v index 6ab7b7f..f1e94cd 100644 --- a/vcs/testbench/sim_top.v +++ b/vcs/testbench/sim_top.v @@ -1,15 +1,18 @@ +import "DPI-C" function void uart_putc( + input byte c +); +import "DPI-C" function byte uart_getc(); + module sim_top( input clock, - input reset, - output uart_valid, - output [7:0] uart_ch + input reset ); wire cpu_clock; wire cpu_reset; wire cpu_memory_0_aw_ready; wire cpu_memory_0_aw_valid; -wire [7:0] cpu_memory_0_aw_bits_id; +wire [6:0] cpu_memory_0_aw_bits_id; wire [39:0] cpu_memory_0_aw_bits_addr; wire [7:0] cpu_memory_0_aw_bits_len; wire [2:0] cpu_memory_0_aw_bits_size; @@ -25,11 +28,11 @@ wire [31:0] cpu_memory_0_w_bits_strb; wire cpu_memory_0_w_bits_last; wire cpu_memory_0_b_ready; wire cpu_memory_0_b_valid; -wire [7:0] cpu_memory_0_b_bits_id; +wire [6:0] cpu_memory_0_b_bits_id; wire [1:0] cpu_memory_0_b_bits_resp; wire cpu_memory_0_ar_ready; wire cpu_memory_0_ar_valid; -wire [7:0] cpu_memory_0_ar_bits_id; +wire [6:0] cpu_memory_0_ar_bits_id; wire [39:0] cpu_memory_0_ar_bits_addr; wire [7:0] cpu_memory_0_ar_bits_len; wire [2:0] cpu_memory_0_ar_bits_size; @@ -40,7 +43,7 @@ wire [2:0] cpu_memory_0_ar_bits_prot; wire [3:0] cpu_memory_0_ar_bits_qos; wire cpu_memory_0_r_ready; wire cpu_memory_0_r_valid; -wire [7:0] cpu_memory_0_r_bits_id; +wire [6:0] cpu_memory_0_r_bits_id; wire [255:0] cpu_memory_0_r_bits_data; wire [1:0] cpu_memory_0_r_bits_resp; wire cpu_memory_0_r_bits_last; @@ -120,55 +123,56 @@ wire [1:0] cpu_dma_0_r_bits_resp; wire cpu_dma_0_r_bits_last; wire [149:0] cpu_io_extIntrs; -wire mmio_clock; -wire mmio_reset; -wire mmio_auto_axi4xbar_in_aw_ready; -wire mmio_auto_axi4xbar_in_aw_valid; -wire [1:0] mmio_auto_axi4xbar_in_aw_bits_id; -wire [30:0] mmio_auto_axi4xbar_in_aw_bits_addr; -wire [7:0] mmio_auto_axi4xbar_in_aw_bits_len; -wire [2:0] mmio_auto_axi4xbar_in_aw_bits_size; -wire [1:0] mmio_auto_axi4xbar_in_aw_bits_burst; -wire mmio_auto_axi4xbar_in_aw_bits_lock; -wire [3:0] mmio_auto_axi4xbar_in_aw_bits_cache; -wire [2:0] mmio_auto_axi4xbar_in_aw_bits_prot; -wire [3:0] mmio_auto_axi4xbar_in_aw_bits_qos; -wire mmio_auto_axi4xbar_in_w_ready; -wire mmio_auto_axi4xbar_in_w_valid; -wire [63:0] mmio_auto_axi4xbar_in_w_bits_data; -wire [7:0] mmio_auto_axi4xbar_in_w_bits_strb; -wire mmio_auto_axi4xbar_in_w_bits_last; -wire mmio_auto_axi4xbar_in_b_ready; -wire mmio_auto_axi4xbar_in_b_valid; -wire [1:0] mmio_auto_axi4xbar_in_b_bits_id; -wire [1:0] mmio_auto_axi4xbar_in_b_bits_resp; -wire mmio_auto_axi4xbar_in_ar_ready; -wire mmio_auto_axi4xbar_in_ar_valid; -wire [1:0] mmio_auto_axi4xbar_in_ar_bits_id; -wire [30:0] mmio_auto_axi4xbar_in_ar_bits_addr; -wire [7:0] mmio_auto_axi4xbar_in_ar_bits_len; -wire [2:0] mmio_auto_axi4xbar_in_ar_bits_size; -wire [1:0] mmio_auto_axi4xbar_in_ar_bits_burst; -wire mmio_auto_axi4xbar_in_ar_bits_lock; -wire [3:0] mmio_auto_axi4xbar_in_ar_bits_cache; -wire [2:0] mmio_auto_axi4xbar_in_ar_bits_prot; -wire [3:0] mmio_auto_axi4xbar_in_ar_bits_qos; -wire mmio_auto_axi4xbar_in_r_ready; -wire mmio_auto_axi4xbar_in_r_valid; -wire [1:0] mmio_auto_axi4xbar_in_r_bits_id; -wire [63:0] mmio_auto_axi4xbar_in_r_bits_data; -wire [1:0] mmio_auto_axi4xbar_in_r_bits_resp; -wire mmio_auto_axi4xbar_in_r_bits_last; -wire mmio_io_uart_out_valid; -wire [7:0] mmio_io_uart_out_ch; -wire mmio_io_uart_in_valid; -wire [7:0] mmio_io_uart_in_ch; +wire mmio_clock; +wire mmio_reset; +wire mmio_io_axi4_0_aw_ready; +wire mmio_io_axi4_0_aw_valid; +wire [1:0] mmio_io_axi4_0_aw_bits_id; +wire [30:0] mmio_io_axi4_0_aw_bits_addr; +wire [7:0] mmio_io_axi4_0_aw_bits_len; +wire [2:0] mmio_io_axi4_0_aw_bits_size; +wire [1:0] mmio_io_axi4_0_aw_bits_burst; +wire mmio_io_axi4_0_aw_bits_lock; +wire [3:0] mmio_io_axi4_0_aw_bits_cache; +wire [2:0] mmio_io_axi4_0_aw_bits_prot; +wire [3:0] mmio_io_axi4_0_aw_bits_qos; +wire mmio_io_axi4_0_w_ready; +wire mmio_io_axi4_0_w_valid; +wire [63:0] mmio_io_axi4_0_w_bits_data; +wire [7:0] mmio_io_axi4_0_w_bits_strb; +wire mmio_io_axi4_0_w_bits_last; +wire mmio_io_axi4_0_b_ready; +wire mmio_io_axi4_0_b_valid; +wire [1:0] mmio_io_axi4_0_b_bits_id; +wire [1:0] mmio_io_axi4_0_b_bits_resp; +wire mmio_io_axi4_0_ar_ready; +wire mmio_io_axi4_0_ar_valid; +wire [1:0] mmio_io_axi4_0_ar_bits_id; +wire [30:0] mmio_io_axi4_0_ar_bits_addr; +wire [7:0] mmio_io_axi4_0_ar_bits_len; +wire [2:0] mmio_io_axi4_0_ar_bits_size; +wire [1:0] mmio_io_axi4_0_ar_bits_burst; +wire mmio_io_axi4_0_ar_bits_lock; +wire [3:0] mmio_io_axi4_0_ar_bits_cache; +wire [2:0] mmio_io_axi4_0_ar_bits_prot; +wire [3:0] mmio_io_axi4_0_ar_bits_qos; +wire mmio_io_axi4_0_r_ready; +wire mmio_io_axi4_0_r_valid; +wire [1:0] mmio_io_axi4_0_r_bits_id; +wire [63:0] mmio_io_axi4_0_r_bits_data; +wire [1:0] mmio_io_axi4_0_r_bits_resp; +wire mmio_io_axi4_0_r_bits_last; +wire mmio_io_uart_out_valid; +wire [7:0] mmio_io_uart_out_ch; +wire mmio_io_uart_in_valid; +wire [7:0] mmio_io_uart_in_ch; +wire [255:0] mmio_io_interrupt_intrVec; wire ram_clock; wire ram_reset; wire ram_auto_in_aw_ready; wire ram_auto_in_aw_valid; -wire [7:0] ram_auto_in_aw_bits_id; +wire [6:0] ram_auto_in_aw_bits_id; wire [39:0] ram_auto_in_aw_bits_addr; wire [7:0] ram_auto_in_aw_bits_len; wire [2:0] ram_auto_in_aw_bits_size; @@ -184,11 +188,11 @@ wire [31:0] ram_auto_in_w_bits_strb; wire ram_auto_in_w_bits_last; wire ram_auto_in_b_ready; wire ram_auto_in_b_valid; -wire [7:0] ram_auto_in_b_bits_id; +wire [6:0] ram_auto_in_b_bits_id; wire [1:0] ram_auto_in_b_bits_resp; wire ram_auto_in_ar_ready; wire ram_auto_in_ar_valid; -wire [7:0] ram_auto_in_ar_bits_id; +wire [6:0] ram_auto_in_ar_bits_id; wire [39:0] ram_auto_in_ar_bits_addr; wire [7:0] ram_auto_in_ar_bits_len; wire [2:0] ram_auto_in_ar_bits_size; @@ -199,7 +203,7 @@ wire [2:0] ram_auto_in_ar_bits_prot; wire [3:0] ram_auto_in_ar_bits_qos; wire ram_auto_in_r_ready; wire ram_auto_in_r_valid; -wire [7:0] ram_auto_in_r_bits_id; +wire [6:0] ram_auto_in_r_bits_id; wire [255:0] ram_auto_in_r_bits_data; wire [1:0] ram_auto_in_r_bits_resp; wire ram_auto_in_r_bits_last; @@ -217,17 +221,17 @@ assign cpu_memory_0_r_bits_id = ram_auto_in_r_bits_id; assign cpu_memory_0_r_bits_data = ram_auto_in_r_bits_data; assign cpu_memory_0_r_bits_resp = ram_auto_in_r_bits_resp; assign cpu_memory_0_r_bits_last = ram_auto_in_r_bits_last; -assign cpu_peripheral_0_aw_ready = mmio_auto_axi4xbar_in_aw_ready; -assign cpu_peripheral_0_w_ready = mmio_auto_axi4xbar_in_w_ready; -assign cpu_peripheral_0_b_valid = mmio_auto_axi4xbar_in_b_valid; -assign cpu_peripheral_0_b_bits_id = mmio_auto_axi4xbar_in_b_bits_id; -assign cpu_peripheral_0_b_bits_resp = mmio_auto_axi4xbar_in_b_bits_resp; -assign cpu_peripheral_0_ar_ready = mmio_auto_axi4xbar_in_ar_ready; -assign cpu_peripheral_0_r_valid = mmio_auto_axi4xbar_in_r_valid; -assign cpu_peripheral_0_r_bits_id = mmio_auto_axi4xbar_in_r_bits_id; -assign cpu_peripheral_0_r_bits_data = mmio_auto_axi4xbar_in_r_bits_data; -assign cpu_peripheral_0_r_bits_resp = mmio_auto_axi4xbar_in_r_bits_resp; -assign cpu_peripheral_0_r_bits_last = mmio_auto_axi4xbar_in_r_bits_last; +assign cpu_peripheral_0_aw_ready = mmio_io_axi4_0_aw_ready; +assign cpu_peripheral_0_w_ready = mmio_io_axi4_0_w_ready; +assign cpu_peripheral_0_b_valid = mmio_io_axi4_0_b_valid; +assign cpu_peripheral_0_b_bits_id = mmio_io_axi4_0_b_bits_id; +assign cpu_peripheral_0_b_bits_resp = mmio_io_axi4_0_b_bits_resp; +assign cpu_peripheral_0_ar_ready = mmio_io_axi4_0_ar_ready; +assign cpu_peripheral_0_r_valid = mmio_io_axi4_0_r_valid; +assign cpu_peripheral_0_r_bits_id = mmio_io_axi4_0_r_bits_id; +assign cpu_peripheral_0_r_bits_data = mmio_io_axi4_0_r_bits_data; +assign cpu_peripheral_0_r_bits_resp = mmio_io_axi4_0_r_bits_resp; +assign cpu_peripheral_0_r_bits_last = mmio_io_axi4_0_r_bits_last; assign cpu_dma_0_aw_valid = 0; assign cpu_dma_0_aw_bits_id = 0; assign cpu_dma_0_aw_bits_addr = 0; @@ -254,38 +258,98 @@ assign cpu_dma_0_ar_bits_cache = 0; assign cpu_dma_0_ar_bits_prot = 0; assign cpu_dma_0_ar_bits_qos = 0; assign cpu_dma_0_r_ready = 0; -assign cpu_io_extIntrs = 0; +assign cpu_io_extIntrs = mmio_io_interrupt_intrVec; +`ifdef NETLIST assign mmio_clock = clock; assign mmio_reset = reset; assign mmio_auto_axi4xbar_in_aw_valid = cpu_peripheral_0_aw_valid; assign mmio_auto_axi4xbar_in_aw_bits_id = cpu_peripheral_0_aw_bits_id; assign mmio_auto_axi4xbar_in_aw_bits_addr = cpu_peripheral_0_aw_bits_addr; -assign mmio_auto_axi4xbar_in_aw_bits_len = cpu_peripheral_0_aw_bits_len; -assign mmio_auto_axi4xbar_in_aw_bits_size = cpu_peripheral_0_aw_bits_size; -assign mmio_auto_axi4xbar_in_aw_bits_burst = cpu_peripheral_0_aw_bits_burst; -assign mmio_auto_axi4xbar_in_aw_bits_lock = cpu_peripheral_0_aw_bits_lock; -assign mmio_auto_axi4xbar_in_aw_bits_cache = cpu_peripheral_0_aw_bits_cache; -assign mmio_auto_axi4xbar_in_aw_bits_prot = cpu_peripheral_0_aw_bits_prot; -assign mmio_auto_axi4xbar_in_aw_bits_qos = cpu_peripheral_0_aw_bits_qos; +assign mmio_auto_axi4xbar_in_aw_bits_len = 8'b0; +assign mmio_auto_axi4xbar_in_aw_bits_size = {1'b0,cpu_peripheral_0_aw_bits_size[1:0]}; +assign mmio_auto_axi4xbar_in_aw_bits_burst = 2'b1; +assign mmio_auto_axi4xbar_in_aw_bits_lock = 1'b0; +assign mmio_auto_axi4xbar_in_aw_bits_cache = 4'b0; +assign mmio_auto_axi4xbar_in_aw_bits_prot = 3'b1; +assign mmio_auto_axi4xbar_in_aw_bits_qos = 4'b0; assign mmio_auto_axi4xbar_in_w_valid = cpu_peripheral_0_w_valid; assign mmio_auto_axi4xbar_in_w_bits_data = cpu_peripheral_0_w_bits_data; assign mmio_auto_axi4xbar_in_w_bits_strb = cpu_peripheral_0_w_bits_strb; -assign mmio_auto_axi4xbar_in_w_bits_last = cpu_peripheral_0_w_bits_last; +assign mmio_auto_axi4xbar_in_w_bits_last = 1'b1; assign mmio_auto_axi4xbar_in_b_ready = cpu_peripheral_0_b_ready; assign mmio_auto_axi4xbar_in_ar_valid = cpu_peripheral_0_ar_valid; assign mmio_auto_axi4xbar_in_ar_bits_id = cpu_peripheral_0_ar_bits_id; assign mmio_auto_axi4xbar_in_ar_bits_addr = cpu_peripheral_0_ar_bits_addr; -assign mmio_auto_axi4xbar_in_ar_bits_len = cpu_peripheral_0_ar_bits_len; -assign mmio_auto_axi4xbar_in_ar_bits_size = cpu_peripheral_0_ar_bits_size; -assign mmio_auto_axi4xbar_in_ar_bits_burst = cpu_peripheral_0_ar_bits_burst; -assign mmio_auto_axi4xbar_in_ar_bits_lock = cpu_peripheral_0_ar_bits_lock; -assign mmio_auto_axi4xbar_in_ar_bits_cache = cpu_peripheral_0_ar_bits_cache; -assign mmio_auto_axi4xbar_in_ar_bits_prot = cpu_peripheral_0_ar_bits_prot; -assign mmio_auto_axi4xbar_in_ar_bits_qos = cpu_peripheral_0_ar_bits_qos; +assign mmio_auto_axi4xbar_in_ar_bits_len = 8'b0; +assign mmio_auto_axi4xbar_in_ar_bits_size = {1'b0,cpu_peripheral_0_ar_bits_size[1:0]}; +assign mmio_auto_axi4xbar_in_ar_bits_burst = 2'b1; +assign mmio_auto_axi4xbar_in_ar_bits_lock = 1'b0; +assign mmio_auto_axi4xbar_in_ar_bits_cache = 4'b0; +assign mmio_auto_axi4xbar_in_ar_bits_prot = 3'b1; +assign mmio_auto_axi4xbar_in_ar_bits_qos = 4'b0; assign mmio_auto_axi4xbar_in_r_ready = cpu_peripheral_0_r_ready; assign mmio_io_uart_in_ch = 8'hff; +assign ram_clock = clock; +assign ram_reset = reset; +assign ram_auto_in_aw_valid = cpu_memory_0_aw_valid; +assign ram_auto_in_aw_bits_id = cpu_memory_0_aw_bits_id; +assign ram_auto_in_aw_bits_addr = {cpu_memory_0_aw_bits_addr[39:6],6'b0}; +assign ram_auto_in_aw_bits_len = {7'b0,cpu_memory_0_aw_bits_len[0]}; +assign ram_auto_in_aw_bits_size = cpu_memory_0_aw_bits_size; +assign ram_auto_in_aw_bits_burst = 2'b1; +assign ram_auto_in_aw_bits_lock = 1'b0; +assign ram_auto_in_aw_bits_cache = 4'b0; +assign ram_auto_in_aw_bits_prot = 3'b1; +assign ram_auto_in_aw_bits_qos = 4'b0; +assign ram_auto_in_w_valid = cpu_memory_0_w_valid; +assign ram_auto_in_w_bits_data = cpu_memory_0_w_bits_data; +assign ram_auto_in_w_bits_strb = cpu_memory_0_w_bits_strb; +assign ram_auto_in_w_bits_last = cpu_memory_0_w_bits_last; +assign ram_auto_in_b_ready = cpu_memory_0_b_ready; +assign ram_auto_in_ar_valid = cpu_memory_0_ar_valid; +assign ram_auto_in_ar_bits_id = cpu_memory_0_ar_bits_id; +assign ram_auto_in_ar_bits_addr = {cpu_memory_0_ar_bits_addr[39:6],6'b0}; +assign ram_auto_in_ar_bits_len = {7'b0,cpu_memory_0_ar_bits_len[0]}; +assign ram_auto_in_ar_bits_size = cpu_memory_0_ar_bits_size; +assign ram_auto_in_ar_bits_burst = 2'b1; +assign ram_auto_in_ar_bits_lock = 1'b0; +assign ram_auto_in_ar_bits_cache = 4'b0; +assign ram_auto_in_ar_bits_prot = 3'b1; +assign ram_auto_in_ar_bits_qos = 4'b0; +assign ram_auto_in_r_ready = cpu_memory_0_r_ready; +`else +assign mmio_clock = clock; +assign mmio_reset = reset; +assign mmio_io_axi4_0_aw_valid = cpu_peripheral_0_aw_valid; +assign mmio_io_axi4_0_aw_bits_id = cpu_peripheral_0_aw_bits_id; +assign mmio_io_axi4_0_aw_bits_addr = cpu_peripheral_0_aw_bits_addr; +assign mmio_io_axi4_0_aw_bits_len = cpu_peripheral_0_aw_bits_len; +assign mmio_io_axi4_0_aw_bits_size = cpu_peripheral_0_aw_bits_size; +assign mmio_io_axi4_0_aw_bits_burst = cpu_peripheral_0_aw_bits_burst; +assign mmio_io_axi4_0_aw_bits_lock = cpu_peripheral_0_aw_bits_lock; +assign mmio_io_axi4_0_aw_bits_cache = cpu_peripheral_0_aw_bits_cache; +assign mmio_io_axi4_0_aw_bits_prot = cpu_peripheral_0_aw_bits_prot; +assign mmio_io_axi4_0_aw_bits_qos = cpu_peripheral_0_aw_bits_qos; +assign mmio_io_axi4_0_w_valid = cpu_peripheral_0_w_valid; +assign mmio_io_axi4_0_w_bits_data = cpu_peripheral_0_w_bits_data; +assign mmio_io_axi4_0_w_bits_strb = cpu_peripheral_0_w_bits_strb; +assign mmio_io_axi4_0_w_bits_last = cpu_peripheral_0_w_bits_last; +assign mmio_io_axi4_0_b_ready = cpu_peripheral_0_b_ready; +assign mmio_io_axi4_0_ar_valid = cpu_peripheral_0_ar_valid; +assign mmio_io_axi4_0_ar_bits_id = cpu_peripheral_0_ar_bits_id; +assign mmio_io_axi4_0_ar_bits_addr = cpu_peripheral_0_ar_bits_addr; +assign mmio_io_axi4_0_ar_bits_len = cpu_peripheral_0_ar_bits_len; +assign mmio_io_axi4_0_ar_bits_size = cpu_peripheral_0_ar_bits_size; +assign mmio_io_axi4_0_ar_bits_burst = cpu_peripheral_0_ar_bits_burst; +assign mmio_io_axi4_0_ar_bits_lock = cpu_peripheral_0_ar_bits_lock; +assign mmio_io_axi4_0_ar_bits_cache = cpu_peripheral_0_ar_bits_cache; +assign mmio_io_axi4_0_ar_bits_prot = cpu_peripheral_0_ar_bits_prot; +assign mmio_io_axi4_0_ar_bits_qos = cpu_peripheral_0_ar_bits_qos; +assign mmio_io_axi4_0_r_ready = cpu_peripheral_0_r_ready; +assign mmio_io_uart_in_ch = 8'hff; + assign ram_clock = clock; assign ram_reset = reset; assign ram_auto_in_aw_valid = cpu_memory_0_aw_valid; @@ -314,15 +378,26 @@ assign ram_auto_in_ar_bits_cache = cpu_memory_0_ar_bits_cache; assign ram_auto_in_ar_bits_prot = cpu_memory_0_ar_bits_prot; assign ram_auto_in_ar_bits_qos = cpu_memory_0_ar_bits_qos; assign ram_auto_in_r_ready = cpu_memory_0_r_ready; +`endif + +always @(posedge clock) begin + if (mmio_io_uart_out_valid) begin + uart_putc(mmio_io_uart_out_ch); + end +end -assign uart_valid = mmio_io_uart_out_valid; -assign uart_ch = mmio_io_uart_out_ch; +`ifdef NETLIST +nanshan_soc_core_XSTop_0 CPU( +`else XSTop CPU( - // .clock(cpu_clock), - // .reset(cpu_reset), +`endif .io_clock(cpu_clock), +`ifdef NETLIST + .io_reset_BAR(~cpu_reset), +`else .io_reset(cpu_reset), +`endif .memory_0_aw_ready(cpu_memory_0_aw_ready), .memory_0_aw_valid(cpu_memory_0_aw_valid), .memory_0_aw_bits_id(cpu_memory_0_aw_bits_id), @@ -435,22 +510,35 @@ XSTop CPU( .dma_0_r_bits_resp(cpu_dma_0_r_bits_resp), .dma_0_r_bits_last(cpu_dma_0_r_bits_last), .io_extIntrs(cpu_io_extIntrs) +`ifdef NETLIST + , + .IN22(1'b0), + .IN23(1'b0), + .IN24(1'b0), + .IN25(1'b0), + .IN26(1'b0), + .IN28(1'b0), + .IN29(1'b0), + .IN0(cpu_clock), + .IN31(1'b0), + .IN27(1'b0) +`endif ); always @(posedge clock) begin - if (mmio_auto_axi4xbar_in_aw_valid) begin - //$display("MMIO: waddr valid %x", mmio_auto_axi4xbar_in_aw_bits_addr); + if (mmio_io_axi4_0_aw_valid) begin + //$display("MMIO: waddr valid %x", mmio_io_axi4_0_aw_bits_addr); end - if (mmio_auto_axi4xbar_in_w_valid) begin - //$display("MMIO: wdata %x", mmio_auto_axi4xbar_in_w_bits_data); + if (mmio_io_axi4_0_w_valid) begin + //$display("MMIO: wdata %x", mmio_io_axi4_0_w_bits_data); end - if (mmio_auto_axi4xbar_in_aw_ready && mmio_auto_axi4xbar_in_aw_valid) begin - //$display("MMIO: waddr %x", mmio_auto_axi4xbar_in_aw_bits_addr); + if (mmio_io_axi4_0_aw_ready && mmio_io_axi4_0_aw_valid) begin + //$display("MMIO: waddr %x", mmio_io_axi4_0_aw_bits_addr); end - if (mmio_auto_axi4xbar_in_w_ready && mmio_auto_axi4xbar_in_w_valid) begin - //$display("MMIO: wdata %x", mmio_auto_axi4xbar_in_w_bits_data); + if (mmio_io_axi4_0_w_ready && mmio_io_axi4_0_w_valid) begin + //$display("MMIO: wdata %x", mmio_io_axi4_0_w_bits_data); end end @@ -459,48 +547,50 @@ end SimMMIO mmio( .clock(mmio_clock), .reset(mmio_reset), - .auto_axi4xbar_in_aw_ready(mmio_auto_axi4xbar_in_aw_ready), - .auto_axi4xbar_in_aw_valid(mmio_auto_axi4xbar_in_aw_valid), - .auto_axi4xbar_in_aw_bits_id(mmio_auto_axi4xbar_in_aw_bits_id), - .auto_axi4xbar_in_aw_bits_addr(mmio_auto_axi4xbar_in_aw_bits_addr), - .auto_axi4xbar_in_aw_bits_len(mmio_auto_axi4xbar_in_aw_bits_len), - .auto_axi4xbar_in_aw_bits_size(mmio_auto_axi4xbar_in_aw_bits_size), - .auto_axi4xbar_in_aw_bits_burst(mmio_auto_axi4xbar_in_aw_bits_burst), - .auto_axi4xbar_in_aw_bits_lock(mmio_auto_axi4xbar_in_aw_bits_lock), - .auto_axi4xbar_in_aw_bits_cache(mmio_auto_axi4xbar_in_aw_bits_cache), - .auto_axi4xbar_in_aw_bits_prot(mmio_auto_axi4xbar_in_aw_bits_prot), - .auto_axi4xbar_in_aw_bits_qos(mmio_auto_axi4xbar_in_aw_bits_qos), - .auto_axi4xbar_in_w_ready(mmio_auto_axi4xbar_in_w_ready), - .auto_axi4xbar_in_w_valid(mmio_auto_axi4xbar_in_w_valid), - .auto_axi4xbar_in_w_bits_data(mmio_auto_axi4xbar_in_w_bits_data), - .auto_axi4xbar_in_w_bits_strb(mmio_auto_axi4xbar_in_w_bits_strb), - .auto_axi4xbar_in_w_bits_last(mmio_auto_axi4xbar_in_w_bits_last), - .auto_axi4xbar_in_b_ready(mmio_auto_axi4xbar_in_b_ready), - .auto_axi4xbar_in_b_valid(mmio_auto_axi4xbar_in_b_valid), - .auto_axi4xbar_in_b_bits_id(mmio_auto_axi4xbar_in_b_bits_id), - .auto_axi4xbar_in_b_bits_resp(mmio_auto_axi4xbar_in_b_bits_resp), - .auto_axi4xbar_in_ar_ready(mmio_auto_axi4xbar_in_ar_ready), - .auto_axi4xbar_in_ar_valid(mmio_auto_axi4xbar_in_ar_valid), - .auto_axi4xbar_in_ar_bits_id(mmio_auto_axi4xbar_in_ar_bits_id), - .auto_axi4xbar_in_ar_bits_addr(mmio_auto_axi4xbar_in_ar_bits_addr), - .auto_axi4xbar_in_ar_bits_len(mmio_auto_axi4xbar_in_ar_bits_len), - .auto_axi4xbar_in_ar_bits_size(mmio_auto_axi4xbar_in_ar_bits_size), - .auto_axi4xbar_in_ar_bits_burst(mmio_auto_axi4xbar_in_ar_bits_burst), - .auto_axi4xbar_in_ar_bits_lock(mmio_auto_axi4xbar_in_ar_bits_lock), - .auto_axi4xbar_in_ar_bits_cache(mmio_auto_axi4xbar_in_ar_bits_cache), - .auto_axi4xbar_in_ar_bits_prot(mmio_auto_axi4xbar_in_ar_bits_prot), - .auto_axi4xbar_in_ar_bits_qos(mmio_auto_axi4xbar_in_ar_bits_qos), - .auto_axi4xbar_in_r_ready(mmio_auto_axi4xbar_in_r_ready), - .auto_axi4xbar_in_r_valid(mmio_auto_axi4xbar_in_r_valid), - .auto_axi4xbar_in_r_bits_id(mmio_auto_axi4xbar_in_r_bits_id), - .auto_axi4xbar_in_r_bits_data(mmio_auto_axi4xbar_in_r_bits_data), - .auto_axi4xbar_in_r_bits_resp(mmio_auto_axi4xbar_in_r_bits_resp), - .auto_axi4xbar_in_r_bits_last(mmio_auto_axi4xbar_in_r_bits_last), + .io_axi4_0_aw_ready(mmio_io_axi4_0_aw_ready), + .io_axi4_0_aw_valid(mmio_io_axi4_0_aw_valid), + .io_axi4_0_aw_bits_id(mmio_io_axi4_0_aw_bits_id), + .io_axi4_0_aw_bits_addr(mmio_io_axi4_0_aw_bits_addr), + .io_axi4_0_aw_bits_len(mmio_io_axi4_0_aw_bits_len), + .io_axi4_0_aw_bits_size(mmio_io_axi4_0_aw_bits_size), + .io_axi4_0_aw_bits_burst(mmio_io_axi4_0_aw_bits_burst), + .io_axi4_0_aw_bits_lock(mmio_io_axi4_0_aw_bits_lock), + .io_axi4_0_aw_bits_cache(mmio_io_axi4_0_aw_bits_cache), + .io_axi4_0_aw_bits_prot(mmio_io_axi4_0_aw_bits_prot), + .io_axi4_0_aw_bits_qos(mmio_io_axi4_0_aw_bits_qos), + .io_axi4_0_w_ready(mmio_io_axi4_0_w_ready), + .io_axi4_0_w_valid(mmio_io_axi4_0_w_valid), + .io_axi4_0_w_bits_data(mmio_io_axi4_0_w_bits_data), + .io_axi4_0_w_bits_strb(mmio_io_axi4_0_w_bits_strb), + .io_axi4_0_w_bits_last(mmio_io_axi4_0_w_bits_last), + .io_axi4_0_b_ready(mmio_io_axi4_0_b_ready), + .io_axi4_0_b_valid(mmio_io_axi4_0_b_valid), + .io_axi4_0_b_bits_id(mmio_io_axi4_0_b_bits_id), + .io_axi4_0_b_bits_resp(mmio_io_axi4_0_b_bits_resp), + .io_axi4_0_ar_ready(mmio_io_axi4_0_ar_ready), + .io_axi4_0_ar_valid(mmio_io_axi4_0_ar_valid), + .io_axi4_0_ar_bits_id(mmio_io_axi4_0_ar_bits_id), + .io_axi4_0_ar_bits_addr(mmio_io_axi4_0_ar_bits_addr), + .io_axi4_0_ar_bits_len(mmio_io_axi4_0_ar_bits_len), + .io_axi4_0_ar_bits_size(mmio_io_axi4_0_ar_bits_size), + .io_axi4_0_ar_bits_burst(mmio_io_axi4_0_ar_bits_burst), + .io_axi4_0_ar_bits_lock(mmio_io_axi4_0_ar_bits_lock), + .io_axi4_0_ar_bits_cache(mmio_io_axi4_0_ar_bits_cache), + .io_axi4_0_ar_bits_prot(mmio_io_axi4_0_ar_bits_prot), + .io_axi4_0_ar_bits_qos(mmio_io_axi4_0_ar_bits_qos), + .io_axi4_0_r_ready(mmio_io_axi4_0_r_ready), + .io_axi4_0_r_valid(mmio_io_axi4_0_r_valid), + .io_axi4_0_r_bits_id(mmio_io_axi4_0_r_bits_id), + .io_axi4_0_r_bits_data(mmio_io_axi4_0_r_bits_data), + .io_axi4_0_r_bits_resp(mmio_io_axi4_0_r_bits_resp), + .io_axi4_0_r_bits_last(mmio_io_axi4_0_r_bits_last), .io_uart_out_valid(mmio_io_uart_out_valid), .io_uart_out_ch(mmio_io_uart_out_ch), .io_uart_in_valid(mmio_io_uart_in_valid), - .io_uart_in_ch(mmio_io_uart_in_ch) + .io_uart_in_ch(mmio_io_uart_in_ch), + .io_interrupt_intrVec(mmio_io_interrupt_intrVec) ); + always @(posedge clock) begin if (ram_auto_in_aw_valid) begin //$display("waddr valid = %x", ram_auto_in_aw_bits_addr); @@ -520,7 +610,7 @@ if (ram_auto_in_ar_valid && ram_auto_in_ar_ready) begin end -AXI4RAM ram( +AXI4RAM_1 ram( .clock(ram_clock), .reset(ram_reset), .auto_in_aw_ready(ram_auto_in_aw_ready), diff --git a/vcs/testbench/tb.v b/vcs/testbench/tb.v index 3512a7a..ae06a48 100644 --- a/vcs/testbench/tb.v +++ b/vcs/testbench/tb.v @@ -1,5 +1,6 @@ import "DPI-C" function void init_ram(); import "DPI-C" function void init_sd(); +import "DPI-C" function void init_uart(); module tb_top(); @@ -13,35 +14,27 @@ initial begin init_sd(); clock = 0; reset = 1; - //$vcdplusfile("fix.vpd"); - //$vcdpluson; + if ($test$plusargs("dump-wave")) begin + $vcdplusfile("fix.vpd"); + $vcdpluson; + end #100 reset = 0; - // #10000 $finish; - //#220000 $vcdplusfile("fix.vpd"); - // $vcdpluson; end always #1 clock = ~clock; sim_top sim ( .clock(clock), - .reset(reset), - .uart_valid(uart_valid), - .uart_ch(uart_ch) + .reset(reset) ); -always @(posedge clock) begin - if (uart_valid && uart_ch) begin - $write("%c", uart_ch); - end -end - reg [63:0] stuck_timer; reg [63:0] commit_count; reg [63:0] cycle_count; -`define ROQ sim.CPU.core.ctrlBlock.roq -`define CSR sim.CPU.core.integerBlock.jmpExeUnit.csr +`define CORE sim.CPU.core +`define ROQ `CORE.ctrlBlock.roq +`define CSR `CORE.integerBlock.jmpExeUnit.csr wire has_commit = !`ROQ.io_commits_isWalk && `ROQ.io_commits_valid_0; @@ -61,8 +54,8 @@ always @(posedge clock) begin else cycle_count <= cycle_count + 1; - if (!reset && stuck_timer > 5000) begin - $display("no instruction commits for 5000 cycles"); + if (!reset && stuck_timer > 2000) begin + $display("no instruction commits for 2000 cycles"); $finish; end if (!reset && !`ROQ.io_commits_isWalk && `ROQ.io_commits_valid_0) begin @@ -78,5 +71,7 @@ always @(posedge clock) begin end end +`include "testbench/force.h" + endmodule diff --git a/vcs/testbench/uart.c b/vcs/testbench/uart.c new file mode 100644 index 0000000..0778ed6 --- /dev/null +++ b/vcs/testbench/uart.c @@ -0,0 +1,70 @@ +#include "common.h" + +#define QUEUE_SIZE 1024 +static char queue[QUEUE_SIZE] = {}; +static int f = 0, r = 0; + +static void uart_enqueue(char ch) { + int next = (r + 1) % QUEUE_SIZE; + if (next != f) { + // not full + queue[r] = ch; + r = next; + } +} + +static int uart_dequeue(void) { + int k = 0; + if (f != r) { + k = queue[f]; + f = (f + 1) % QUEUE_SIZE; + } else { + static int last = 0; + k = "root\n"[last ++]; + if (last == 5) last = 0; + // generate a random key every 1s for pal + //k = -1;//"uiojkl"[rand()% 6]; + } + return k; +} + +uint8_t uart_getc() { + static uint32_t lasttime = 0; + + uint8_t ch = -1; + return ch; +} + +void uart_putc(char c) { + printf("%c", c); + fflush(stdout); +} + +static void preset_input() { + char rtthread_cmd[128] = "memtrace\n"; + char init_cmd[128] = "2" // choose PAL + "jjjjjjjkkkkkk" // walk to enemy + ; + char busybox_cmd[128] = + "ls\n" + "echo 123\n" + "cd /root/benchmark\n" + "ls\n" + "./stream\n" + "ls\n" + "cd /root/redis\n" + "ls\n" + "ifconfig -a\n" + "./redis-server\n"; + char debian_cmd[128] = "root\n"; + char *buf = debian_cmd; + int i; + for (i = 0; i < strlen(buf); i ++) { + uart_enqueue(buf[i]); + } +} + +void init_uart(void) { + preset_input(); +} +