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Merge branch 'main' of https://github.com/OpenXiangShan/env-scripts i…
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@Lemover
Lemover committed Jun 2, 2021
2 parents ede4656 + 78afc39 commit 5becdf5
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12 changes: 4 additions & 8 deletions vcs/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -7,24 +7,20 @@ VCS_SRC_FILE = $(shell find $(RTL_DIR) -name "*.v")
VCS_TB_DIR = $(abspath ./testbench)
VCS_TB_FILE = $(shell find $(VCS_TB_DIR) -name "*.c") \
$(shell find $(VCS_TB_DIR) -name "*.v")
VCS_OTHER_FILE = $(shell find $(VCS_TB_DIR) -name "*.h")

VCS_OPTS := -full64 +v2k -timescale=1ns/1ns \
-LDFLAGS -Wl,--no-as-needed \
-sverilog \
-j200 -sverilog +error+1 \
-debug_access+all \
+lint=TFIPC-L \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+RANDOMIZE_INVALID_ASSIGN \
+define+RANDOMIZE_MEM_INIT \
+define+RANDOMIZE_DELAY=0 \
+define+RANDOMIZE_REG_INIT \
+define+UNIT_DELAY \
+define+no_warning \
-f nanshan.f \
-f sram.f

$(EMU_VCS): $(VCS_SRC_FILE) $(VCS_TB_FILE)
export RTL_PATH=$(RTL_DIR) && export LIB_PATH=$(LIB_DIR) && export LIB_PREFIX="tt0p9v85c.v" && vcs $(VCS_OPTS) $(VCS_TB_FILE)
$(EMU_VCS): $(VCS_SRC_FILE) $(VCS_TB_FILE) $(VCS_OTHER_FILE)
export RTL_PATH=$(RTL_DIR) && export LIB_PATH=$(LIB_DIR) && export LIB_PREFIX="tt1v25c.v" && vcs $(VCS_OPTS) $(VCS_TB_FILE)

clean:
rm -rf simv csrc DVEfiles simv.daidir stack.info.* ucli.key
Expand Down
288 changes: 128 additions & 160 deletions vcs/testbench/AXI4RAM/AXI4RAM.v → vcs/testbench/AXI4RAM_1/AXI4RAM_1.v
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1 change: 1 addition & 0 deletions vcs/testbench/AXI4RAM/RAMHelper.v → vcs/testbench/AXI4RAM_1/RAMHelper.v
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Original file line number Diff line number Diff line change
Expand Up @@ -28,3 +28,4 @@ module RAMHelper(
end

endmodule

112 changes: 40 additions & 72 deletions vcs/testbench/SimMMIO/AXI4DummySD.v
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Original file line number Diff line number Diff line change
Expand Up @@ -62,22 +62,22 @@ module AXI4DummySD(
wire [31:0] sdHelper_data; // @[AXI4DummySD.scala 108:26]
wire sdHelper_setAddr; // @[AXI4DummySD.scala 108:26]
wire [31:0] sdHelper_addr; // @[AXI4DummySD.scala 108:26]
reg [1:0] state; // @[AXI4SlaveModule.scala 80:22]
wire _T_61 = state == 2'h0; // @[AXI4SlaveModule.scala 138:24]
wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 138:24]
reg [1:0] state; // @[AXI4SlaveModule.scala 79:22]
wire _T_61 = state == 2'h0; // @[AXI4SlaveModule.scala 137:24]
wire in_ar_ready = state == 2'h0; // @[AXI4SlaveModule.scala 137:24]
wire in_ar_valid = auto_in_ar_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire _T = in_ar_ready & in_ar_valid; // @[Decoupled.scala 40:37]
wire in_aw_ready = _T_61 & ~in_ar_valid; // @[AXI4SlaveModule.scala 156:35]
wire in_aw_ready = _T_61 & ~in_ar_valid; // @[AXI4SlaveModule.scala 155:35]
wire in_aw_valid = auto_in_aw_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire _T_1 = in_aw_ready & in_aw_valid; // @[Decoupled.scala 40:37]
wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 157:23]
wire in_w_ready = state == 2'h2; // @[AXI4SlaveModule.scala 156:23]
wire in_w_valid = auto_in_w_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire _T_2 = in_w_ready & in_w_valid; // @[Decoupled.scala 40:37]
wire in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 160:22]
wire in_b_valid = state == 2'h3; // @[AXI4SlaveModule.scala 159:22]
wire _T_3 = in_b_ready & in_b_valid; // @[Decoupled.scala 40:37]
wire in_r_ready = auto_in_r_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 140:23]
wire in_r_valid = state == 2'h1; // @[AXI4SlaveModule.scala 139:23]
wire _T_4 = in_r_ready & in_r_valid; // @[Decoupled.scala 40:37]
wire [1:0] in_aw_bits_burst = auto_in_aw_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire [1:0] in_ar_bits_burst = auto_in_ar_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
Expand All @@ -87,26 +87,26 @@ module AXI4DummySD(
wire [7:0] in_ar_bits_len = auto_in_ar_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
reg [7:0] r; // @[Reg.scala 27:20]
wire [7:0] _T_43 = _T ? in_ar_bits_len : r; // @[Hold.scala 7:48]
wire in_r_bits_last = value == _T_43; // @[AXI4SlaveModule.scala 118:32]
wire in_r_bits_last = value == _T_43; // @[AXI4SlaveModule.scala 117:32]
wire _T_21 = 2'h2 == state; // @[Conditional.scala 37:30]
wire in_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 97:42 AXI4SlaveModule.scala 98:15 AXI4SlaveModule.scala 80:22]
wire [1:0] _GEN_3 = _T_2 & in_w_bits_last ? 2'h3 : state; // @[AXI4SlaveModule.scala 96:42 AXI4SlaveModule.scala 97:15 AXI4SlaveModule.scala 79:22]
wire _T_24 = 2'h3 == state; // @[Conditional.scala 37:30]
wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 102:24 AXI4SlaveModule.scala 103:15 AXI4SlaveModule.scala 80:22]
wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 80:22]
wire [1:0] _GEN_4 = _T_3 ? 2'h0 : state; // @[AXI4SlaveModule.scala 101:24 AXI4SlaveModule.scala 102:15 AXI4SlaveModule.scala 79:22]
wire [1:0] _GEN_5 = _T_24 ? _GEN_4 : state; // @[Conditional.scala 39:67 AXI4SlaveModule.scala 79:22]
wire [7:0] in_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
reg [30:0] r_1; // @[Reg.scala 27:20]
wire [30:0] in_ar_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire [30:0] _GEN_10 = _T ? in_ar_bits_addr : r_1; // @[Reg.scala 28:19 Reg.scala 28:23 Reg.scala 27:20]
wire [7:0] _value_T_1 = value + 8'h1; // @[Counter.scala 76:24]
wire _T_50 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 129:26]
wire _T_51 = in_ar_bits_len == 8'h0 | _T_50; // @[AXI4SlaveModule.scala 128:32]
wire _T_52 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 130:26]
wire _T_53 = _T_51 | _T_52; // @[AXI4SlaveModule.scala 129:34]
wire _T_54 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 131:26]
wire _T_55 = _T_53 | _T_54; // @[AXI4SlaveModule.scala 130:34]
wire _T_56 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 132:26]
wire _T_57 = _T_55 | _T_56; // @[AXI4SlaveModule.scala 131:34]
wire _T_50 = in_ar_bits_len == 8'h1; // @[AXI4SlaveModule.scala 128:26]
wire _T_51 = in_ar_bits_len == 8'h0 | _T_50; // @[AXI4SlaveModule.scala 127:32]
wire _T_52 = in_ar_bits_len == 8'h3; // @[AXI4SlaveModule.scala 129:26]
wire _T_53 = _T_51 | _T_52; // @[AXI4SlaveModule.scala 128:34]
wire _T_54 = in_ar_bits_len == 8'h7; // @[AXI4SlaveModule.scala 130:26]
wire _T_55 = _T_53 | _T_54; // @[AXI4SlaveModule.scala 129:34]
wire _T_56 = in_ar_bits_len == 8'hf; // @[AXI4SlaveModule.scala 131:26]
wire _T_57 = _T_55 | _T_56; // @[AXI4SlaveModule.scala 130:34]
reg [30:0] r_2; // @[Reg.scala 27:20]
wire [30:0] in_aw_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire [30:0] _GEN_13 = _T_1 ? in_aw_bits_addr : r_2; // @[Reg.scala 28:19 Reg.scala 28:23 Reg.scala 27:20]
Expand Down Expand Up @@ -211,16 +211,16 @@ module AXI4DummySD(
wire [3:0] in_aw_bits_cache = auto_in_aw_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire [2:0] in_aw_bits_prot = auto_in_aw_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire [3:0] in_aw_bits_qos = auto_in_aw_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire [1:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 162:16]
wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 159:18]
wire [1:0] in_b_bits_id = r_3; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 161:16]
wire [1:0] in_b_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 158:18]
wire [2:0] in_ar_bits_size = auto_in_ar_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire in_ar_bits_lock = auto_in_ar_bits_lock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire [3:0] in_ar_bits_cache = auto_in_ar_bits_cache; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire [2:0] in_ar_bits_prot = auto_in_ar_bits_prot; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire [3:0] in_ar_bits_qos = auto_in_ar_bits_qos; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
wire [1:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 164:16]
wire [1:0] in_r_bits_id = r_5; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 163:16]
wire [63:0] in_r_bits_data = {hi_2,hi_2}; // @[Cat.scala 30:58]
wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 139:18]
wire [1:0] in_r_bits_resp = 2'h0; // @[Nodes.scala 1210:84 AXI4SlaveModule.scala 138:18]
SDHelper sdHelper ( // @[AXI4DummySD.scala 108:26]
.clk(sdHelper_clk),
.ren(sdHelper_ren),
Expand All @@ -244,17 +244,17 @@ module AXI4DummySD(
assign sdHelper_setAddr = _T_2 & _GEN_13[12:0] == 13'h0 & _GEN_38; // @[RegMap.scala 14:48]
assign sdHelper_addr = regs_1; // @[AXI4DummySD.scala 112:22]
always @(posedge clock) begin
if (reset) begin // @[AXI4SlaveModule.scala 80:22]
state <= 2'h0; // @[AXI4SlaveModule.scala 80:22]
if (reset) begin // @[AXI4SlaveModule.scala 79:22]
state <= 2'h0; // @[AXI4SlaveModule.scala 79:22]
end else if (_T_15) begin // @[Conditional.scala 40:58]
if (_T_1) begin // @[AXI4SlaveModule.scala 87:25]
state <= 2'h2; // @[AXI4SlaveModule.scala 88:15]
end else if (_T) begin // @[AXI4SlaveModule.scala 84:25]
state <= 2'h1; // @[AXI4SlaveModule.scala 85:15]
if (_T_1) begin // @[AXI4SlaveModule.scala 86:25]
state <= 2'h2; // @[AXI4SlaveModule.scala 87:15]
end else if (_T) begin // @[AXI4SlaveModule.scala 83:25]
state <= 2'h1; // @[AXI4SlaveModule.scala 84:15]
end
end else if (_T_18) begin // @[Conditional.scala 39:67]
if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 92:42]
state <= 2'h0; // @[AXI4SlaveModule.scala 93:15]
if (_T_4 & in_r_bits_last) begin // @[AXI4SlaveModule.scala 91:42]
state <= 2'h0; // @[AXI4SlaveModule.scala 92:15]
end
end else if (_T_21) begin // @[Conditional.scala 39:67]
state <= _GEN_3;
Expand All @@ -263,9 +263,9 @@ module AXI4DummySD(
end
if (reset) begin // @[Counter.scala 60:40]
value <= 8'h0; // @[Counter.scala 60:40]
end else if (_T_4) begin // @[AXI4SlaveModule.scala 120:23]
if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 122:28]
value <= 8'h0; // @[AXI4SlaveModule.scala 123:17]
end else if (_T_4) begin // @[AXI4SlaveModule.scala 119:23]
if (in_r_bits_last) begin // @[AXI4SlaveModule.scala 121:28]
value <= 8'h0; // @[AXI4SlaveModule.scala 122:17]
end else begin
value <= _value_T_1; // @[Counter.scala 76:15]
end
Expand Down Expand Up @@ -366,70 +366,37 @@ module AXI4DummySD(
`endif
if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin
$fwrite(32'h80000002,
"Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:72 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n"
); // @[AXI4SlaveModule.scala 72:11]
"Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:71 assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n"
); // @[AXI4SlaveModule.scala 71:11]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1 & ~(in_aw_bits_burst == 2'h1 | reset)) begin
$fatal; // @[AXI4SlaveModule.scala 72:11]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin
$fwrite(32'h80000002,
"Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:75 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n"
); // @[AXI4SlaveModule.scala 75:11]
"Assertion failed: only support busrt ince!\n at AXI4SlaveModule.scala:74 assert(in.ar.bits.burst === AXI4Parameters.BURST_INCR, \"only support busrt ince!\")\n"
); // @[AXI4SlaveModule.scala 74:11]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T & ~(in_ar_bits_burst == 2'h1 | reset)) begin
$fatal; // @[AXI4SlaveModule.scala 75:11]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T & ~(_T_57 | reset)) begin
$fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:127 assert(\n"); // @[AXI4SlaveModule.scala 127:13]
$fwrite(32'h80000002,"Assertion failed\n at AXI4SlaveModule.scala:126 assert(\n"); // @[AXI4SlaveModule.scala 126:13]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T & ~(_T_57 | reset)) begin
$fatal; // @[AXI4SlaveModule.scala 127:13]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
Expand Down Expand Up @@ -507,3 +474,4 @@ end // initial
`endif
`endif // SYNTHESIS
endmodule

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