diff --git a/src/isa/riscv64/instr/rvv/vreg_impl.c b/src/isa/riscv64/instr/rvv/vreg_impl.c
index 3dfdd369d..548147912 100644
--- a/src/isa/riscv64/instr/rvv/vreg_impl.c
+++ b/src/isa/riscv64/instr/rvv/vreg_impl.c
@@ -93,7 +93,8 @@ int get_vlmax(int vsew, int vlmul) {
       default: panic("Unexpected vlmul\n");
     }
   } else {
-    panic("vlmul = 4 is reserved\n");
+    Loge("vlmul = 4 is reserved\n");
+    return -1;
   }
 }