rv64v: fix four bugs discovered by riscv-vector-intrinsic-fuzzing

[NewPaulWalker]

1. fix align bug in the set_vreg of vld. Align is based on eew and emul, not just sew and lmul.
2. fix a bug in the vmsbf. It generated redundant assign for the rule 'when there are no active 1 in the source, set all active elements in the destination to 1'. This rule was already ensured by the for loop, and this way would overwrite non-active elements in destnation.
3. for f16_to_i8 vfncvt, add processing path for it.
4. for i8_to_f16 vfwcvt, add processing path for it, and delete redundant convert assign in i16_to_f32 and i32_to_f64.