From 875cfbbde31dc40ab9a5f911e83959de618c3d04 Mon Sep 17 00:00:00 2001 From: anandaravuri Date: Mon, 16 Oct 2023 15:21:39 -0700 Subject: [PATCH 1/4] Fix: Update HE Cache bias command line input MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit -Change HE Cache bias command line to –bias host or device -Change scenario setup message to “Pretest scenario started..” and actual test message Test started ......" -Change Fails to allocate 2MB huge page: Invalid argument to “Failed to allocate 2MB huge page: Invalid argument” -Fix output message “number of nodes on system” -Set Stride value only if user passes command line --stride value. Signed-off-by: anandaravuri --- samples/cxl_host_exerciser/cxl_he_cache_cmd.h | 77 ++++++++++++------- samples/cxl_host_exerciser/cxl_he_cmd.h | 56 ++++++++------ .../cxl_host_exerciser/cxl_host_exerciser.h | 5 +- samples/cxl_host_exerciser/he_cache_test.h | 10 +-- 4 files changed, 91 insertions(+), 57 deletions(-) diff --git a/samples/cxl_host_exerciser/cxl_he_cache_cmd.h b/samples/cxl_host_exerciser/cxl_he_cache_cmd.h index 2945ba23810e..c58eb6fccfe9 100644 --- a/samples/cxl_host_exerciser/cxl_he_cache_cmd.h +++ b/samples/cxl_host_exerciser/cxl_he_cache_cmd.h @@ -50,7 +50,8 @@ class he_cache_cmd : public he_cmd { public: he_cache_cmd() : he_continuousmode_(false), he_contmodetime_(0), he_linerep_count_(0), - he_stide_(0), he_test_(0), he_test_all_(false), he_dev_instance_(0) {} + he_stide_(0), he_test_(0), he_test_all_(false), he_dev_instance_(0), + he_stide_cmd_(false) {} virtual ~he_cache_cmd() {} @@ -94,9 +95,9 @@ class he_cache_cmd : public he_cmd { ->default_val("host"); app->add_option("--bias", he_bias_, - "host exerciser run on hostmem or fpgamem") + "host exerciser run on host or device") ->transform(CLI::CheckedTransformer(he_bias)) - ->default_val("hostmem"); + ->default_val("host"); // device cache0 or cache1 app->add_option("--device", he_dev_instance_, @@ -138,9 +139,6 @@ class he_cache_cmd : public he_cmd { he_info_.value = host_exe_->read64(HE_INFO); host_exe_->write64(HE_RD_NUM_LINES, FPGA_512CACHE_LINES); - // Set Stride to 3 for FPGA read/write cache hit/miss - he_stide_ = 3; - cout << "Read number Lines:" << FPGA_512CACHE_LINES << endl; cout << "Line Repeat Count:" << he_linerep_count_ << endl; cout << "Read address table size:" << he_info_.read_addr_table_size << endl; @@ -155,9 +153,13 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL rd_table_ctl_.value = 0; - if (he_stide_ > 0) { + if (he_stide_cmd_) { rd_table_ctl_.enable_address_stride = 1; rd_table_ctl_.stride = he_stide_; + } else { + // Set Stride to 3 for FPGA read/write cache hit/miss + rd_table_ctl_.enable_address_stride = 1; + rd_table_ctl_.stride = 3; } host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); @@ -178,7 +180,7 @@ class he_cache_cmd : public he_cmd { he_start_test(); // wait for completion - if (!he_wait_test_completion()) { + if (!he_wait_test_completion(HE_PRTEST_SCENARIO)) { he_perf_counters(); host_exerciser_errors(); host_exe_->free_cache_read(); @@ -200,9 +202,13 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL rd_table_ctl_.value = 0; - if (he_stide_ > 0) { + if (he_stide_cmd_) { rd_table_ctl_.enable_address_stride = 1; rd_table_ctl_.stride = he_stide_; + } else { + // Set Stride to 3 for FPGA read/write cache hit/miss + rd_table_ctl_.enable_address_stride = 1; + rd_table_ctl_.stride = 3; } host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); @@ -248,9 +254,6 @@ class he_cache_cmd : public he_cmd { he_info_.value = host_exe_->read64(HE_INFO); host_exe_->write64(HE_RD_NUM_LINES, FPGA_512CACHE_LINES); - // Set Stride to 3 for FPGA read/write cache hit/miss - he_stide_ = 3; - cout << "Read/write number Lines:" << FPGA_512CACHE_LINES << endl; cout << "Line Repeat Count:" << he_linerep_count_ << endl; cout << "Read address table size:" << he_info_.read_addr_table_size << endl; @@ -266,9 +269,13 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL rd_table_ctl_.value = 0; - if (he_stide_ > 0) { + if (he_stide_cmd_) { rd_table_ctl_.enable_address_stride = 1; rd_table_ctl_.stride = he_stide_; + } else { + // Set Stride to 3 for FPGA read/write cache hit/miss + rd_table_ctl_.enable_address_stride = 1; + rd_table_ctl_.stride = 3; } host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); @@ -289,7 +296,7 @@ class he_cache_cmd : public he_cmd { he_start_test(); // wait for completion - if (!he_wait_test_completion()) { + if (!he_wait_test_completion(HE_PRTEST_SCENARIO)) { he_perf_counters(); host_exerciser_errors(); host_exe_->free_cache_read_write(); @@ -317,9 +324,13 @@ class he_cache_cmd : public he_cmd { // Set WR_ADDR_TABLE_CTRL wr_table_ctl_.value = 0; - if (he_stide_ > 0) { + if (he_stide_cmd_) { wr_table_ctl_.enable_address_stride = 1; wr_table_ctl_.stride = he_stide_; + } else { + // Set Stride to 3 for FPGA read/write cache hit/miss + wr_table_ctl_.enable_address_stride = 1; + wr_table_ctl_.stride = 3; } host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, wr_table_ctl_.value); host_exe_->write64(HE_WR_NUM_LINES, FPGA_512CACHE_LINES); @@ -364,9 +375,6 @@ class he_cache_cmd : public he_cmd { he_info_.value = host_exe_->read64(HE_INFO); host_exe_->write64(HE_RD_NUM_LINES, FPGA_512CACHE_LINES); - // Set Stride to 3 for FPGA read/write cache hit/miss - he_stide_ = 3; - cout << "Read number Lines:" << FPGA_512CACHE_LINES << endl; cout << "Line Repeat Count:" << he_linerep_count_ << endl; cout << "Read address table size:" << he_info_.read_addr_table_size << endl; @@ -380,9 +388,13 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL rd_table_ctl_.value = 0; - if (he_stide_ > 0) { + if (he_stide_cmd_) { rd_table_ctl_.enable_address_stride = 1; rd_table_ctl_.stride = he_stide_; + } else { + // Set Stride to 3 for FPGA read/write cache hit/miss + rd_table_ctl_.enable_address_stride = 1; + rd_table_ctl_.stride = 3; } host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); @@ -437,9 +449,6 @@ class he_cache_cmd : public he_cmd { he_info_.value = host_exe_->read64(HE_INFO); host_exe_->write64(HE_WR_NUM_LINES, FPGA_512CACHE_LINES); - // Set Stride to 3 for FPGA read/write cache hit/miss - he_stide_ = 0x3; - cout << "Read/write number Lines:" << FPGA_512CACHE_LINES << endl; cout << "Line Repeat Count:" << he_linerep_count_ << endl; cout << "Read address table size:" << he_info_.read_addr_table_size << endl; @@ -455,9 +464,13 @@ class he_cache_cmd : public he_cmd { // Set WR_ADDR_TABLE_CTRL wr_table_ctl_.value = 0; - if (he_stide_ > 0) { + if (he_stide_cmd_) { wr_table_ctl_.enable_address_stride = 1; wr_table_ctl_.stride = he_stide_; + } else { + // Set Stride to 3 for FPGA read/write cache hit/miss + wr_table_ctl_.enable_address_stride = 1; + wr_table_ctl_.stride = 3; } host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, wr_table_ctl_.value); @@ -527,7 +540,7 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL rd_table_ctl_.value = 0; - if (he_stide_ > 0) { + if (he_stide_cmd_) { rd_table_ctl_.enable_address_stride = 1; rd_table_ctl_.stride = he_stide_; } @@ -611,7 +624,7 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL wr_table_ctl_.value = 0; - if (he_stide_ > 0) { + if (he_stide_cmd_) { wr_table_ctl_.enable_address_stride = 1; wr_table_ctl_.stride = he_stide_; } @@ -692,7 +705,7 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTR rd_table_ctl_.value = 0; - if (he_stide_ > 0) { + if (he_stide_cmd_) { rd_table_ctl_.enable_address_stride = 1; rd_table_ctl_.stride = he_stide_; } @@ -765,7 +778,7 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTR wr_table_ctl_.value = 0; - if (he_stide_ > 0) { + if (he_stide_cmd_) { wr_table_ctl_.enable_address_stride = 1; wr_table_ctl_.stride = he_stide_; } @@ -818,6 +831,11 @@ class he_cache_cmd : public he_cmd { cout << "numa nodes are available set numa node to 0" << endl; }; + CLI::Option* opt = app->get_option_no_throw("--stride"); + if (opt && opt->count() == 1) { + he_stide_cmd_ = true; + } + // reset HE cache he_ctl_.value = 0; he_ctl_.ResetL = 0; @@ -828,6 +846,10 @@ class he_cache_cmd : public he_cmd { print_csr(); + if (!he_set_bias_mode()) { + return -1; + } + if (he_test_all_ == true) { int retvalue = 0; ret = he_run_fpga_rd_cache_hit_test(); @@ -919,6 +941,7 @@ class he_cache_cmd : public he_cmd { uint32_t he_test_; bool he_test_all_; uint32_t he_dev_instance_; + bool he_stide_cmd_; }; void he_cache_thread(uint8_t *buf_ptr, uint64_t len) { diff --git a/samples/cxl_host_exerciser/cxl_he_cmd.h b/samples/cxl_host_exerciser/cxl_he_cmd.h index ae6fc6e68965..ba083c1e6308 100644 --- a/samples/cxl_host_exerciser/cxl_he_cmd.h +++ b/samples/cxl_host_exerciser/cxl_he_cmd.h @@ -32,6 +32,9 @@ #include "cxl_host_exerciser.h" #include "he_cache_test.h" +#define HE_TEST_STARTED "Test started ......" +#define HE_PRTEST_SCENARIO "Pretest scenario started ......" + namespace host_exerciser { class he_cmd : public test_command { @@ -223,11 +226,11 @@ class he_cmd : public test_command { return 0; } - bool he_wait_test_completion() { + bool he_wait_test_completion(const char* str = HE_TEST_STARTED) { /* Wait for test completion */ uint32_t timeout = HELPBK_TEST_TIMEOUT; - cout << "Test started ......" << endl; + cout << str << endl; volatile uint8_t *status_ptr = host_exe_->get_dsm(); while (0 == ((*status_ptr) & 0x1)) { usleep(HELPBK_TEST_SLEEP_INVL); @@ -239,29 +242,38 @@ class he_cmd : public test_command { return true; } - void he_start_test() { - // start test + bool he_set_bias_mode() { - switch (he_bias_) { - case HOSTMEM_BIAS: - he_ctl_.bias_support = 0x0; - break; + // Target memory HOST set BIAS host + if (he_target_ == HE_TARGET_HOST) { + he_ctl_.bias_support = HOSTMEM_BIAS; + // Target memory FPGA set BIAS host/device + if (he_bias_ == HOSTMEM_BIAS) { + he_ctl_.bias_support = HOSTMEM_BIAS; + } else { + cerr << "Invalid configuration:Target memory host and bias device" + << endl; + return false; + } + } else { + // Target memory FPGA set BIAS host/device + if (he_bias_ == HOSTMEM_BIAS) { + he_ctl_.bias_support = FPGAMEM_HOST_BIAS; + } else { + he_ctl_.bias_support = FPGAMEM_DEVICE_BIAS; + } + } - case FPGAMEM_HOST_BIAS: - he_ctl_.bias_support = 0x2; - break; + return true; + } - case FPGAMEM_DEVICE_BIAS: - he_ctl_.bias_support = 0x3; - break; - default: - he_ctl_.bias_support = 0x0; - } - he_ctl_.Start = 0; - host_exe_->write64(HE_CTL, he_ctl_.value); - he_ctl_.Start = 1; - host_exe_->write64(HE_CTL, he_ctl_.value); + void he_start_test() { + // start test + he_ctl_.Start = 0; + host_exe_->write64(HE_CTL, he_ctl_.value); + he_ctl_.Start = 1; + host_exe_->write64(HE_CTL, he_ctl_.value); } bool verify_numa_node() { @@ -272,7 +284,7 @@ class he_cmd : public test_command { } int n = numa_max_node(); - cout << "There are %d nodes on your system:" << n + 1 << endl; + cout << "Number nodes on system:" << n + 1 << endl; int numa_node = numa_node_of_cpu(sched_getcpu()); cout << "HE Cache app numa node:" << numa_node << endl; diff --git a/samples/cxl_host_exerciser/cxl_host_exerciser.h b/samples/cxl_host_exerciser/cxl_host_exerciser.h index a406e7cc5449..d2eaeaac8a73 100644 --- a/samples/cxl_host_exerciser/cxl_host_exerciser.h +++ b/samples/cxl_host_exerciser/cxl_host_exerciser.h @@ -334,9 +334,8 @@ const std::map he_targets = { // Bias support const std::map he_bias = { - {"hostmem", HOSTMEM_BIAS}, - {"fpgamem_host_bias", FPGAMEM_HOST_BIAS}, - {"fpgamem_device_bias", FPGAMEM_DEVICE_BIAS}, + {"host", HOSTMEM_BIAS}, + {"device", FPGAMEM_DEVICE_BIAS}, }; // he cxl cache device instance diff --git a/samples/cxl_host_exerciser/he_cache_test.h b/samples/cxl_host_exerciser/he_cache_test.h index 1d105fb5c5d9..03d006689e59 100644 --- a/samples/cxl_host_exerciser/he_cache_test.h +++ b/samples/cxl_host_exerciser/he_cache_test.h @@ -456,7 +456,7 @@ class afu { logger_->set_level(spdlog::level::from_str(log_level_)); current_command_ = test; if (find_dev_feature() != 0) { - cerr << "fails to find feature" << endl; + cerr << "Failed to find feature" << endl; return exit_codes::exception; }; @@ -536,7 +536,7 @@ class afu { memset(&dma_map, 0, sizeof(dma_map)); if (!buffer_allocate(&ptr, len, numa_node)) { - cerr << "Fails to allocate 4k huge page:" << strerror(errno) << endl; + cerr << "Failed to allocate 4k huge page:" << strerror(errno) << endl; return false; } @@ -610,7 +610,7 @@ class afu { memset(&dma_map, 0, sizeof(dma_map)); if (!buffer_allocate(&ptr, len, numa_node)) { - cerr << "Fails to allocate 2MB huge page:" << strerror(errno) << endl; + cerr << "Failed to allocate 2MB huge page:" << strerror(errno) << endl; return false; } cout << "Read buffer numa node: " << numa_node << endl; @@ -678,7 +678,7 @@ class afu { memset(&dma_map, 0, sizeof(dma_map)); if (!buffer_allocate(&ptr, len, numa_node)) { - cerr << "Fails to allocate 2MB huge page:" << strerror(errno) << endl; + cerr << "Failed to allocate 2MB huge page:" << strerror(errno) << endl; return false; } @@ -746,7 +746,7 @@ class afu { memset(&dma_map, 0, sizeof(dma_map)); if (!buffer_allocate(&ptr, len, numa_node)) { - cerr << "Fails to allocate 2MB huge page:" << strerror(errno) << endl; + cerr << "Failed to allocate 2MB huge page:" << strerror(errno) << endl; return false; } cout << "Read/Write buffer numa node: " << numa_node << endl; From c2c54886e1d6dc39095f48755c296938c9c9c2c9 Mon Sep 17 00:00:00 2001 From: anandaravuri Date: Mon, 16 Oct 2023 19:34:35 -0700 Subject: [PATCH 2/4] fix: he-cache stride typo Signed-off-by: anandaravuri --- samples/cxl_host_exerciser/cxl_he_cache_cmd.h | 52 +++++++++---------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/samples/cxl_host_exerciser/cxl_he_cache_cmd.h b/samples/cxl_host_exerciser/cxl_he_cache_cmd.h index c58eb6fccfe9..34bbcf6d7740 100644 --- a/samples/cxl_host_exerciser/cxl_he_cache_cmd.h +++ b/samples/cxl_host_exerciser/cxl_he_cache_cmd.h @@ -50,8 +50,8 @@ class he_cache_cmd : public he_cmd { public: he_cache_cmd() : he_continuousmode_(false), he_contmodetime_(0), he_linerep_count_(0), - he_stide_(0), he_test_(0), he_test_all_(false), he_dev_instance_(0), - he_stide_cmd_(false) {} + he_stride_(0), he_test_(0), he_test_all_(false), he_dev_instance_(0), + he_stride_cmd_(false) {} virtual ~he_cache_cmd() {} @@ -107,7 +107,7 @@ class he_cache_cmd : public he_cmd { ->default_val("/dev/dfl-cxl-cache.0"); // Set sride - app->add_option("--stride", he_stide_, "Set stride value") + app->add_option("--stride", he_stride_, "Set stride value") ->transform(CLI::Range(0, 3))->default_val("0"); // Line repeat count @@ -153,9 +153,9 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL rd_table_ctl_.value = 0; - if (he_stide_cmd_) { + if (he_stride_cmd_) { rd_table_ctl_.enable_address_stride = 1; - rd_table_ctl_.stride = he_stide_; + rd_table_ctl_.stride = he_stride_; } else { // Set Stride to 3 for FPGA read/write cache hit/miss rd_table_ctl_.enable_address_stride = 1; @@ -202,9 +202,9 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL rd_table_ctl_.value = 0; - if (he_stide_cmd_) { + if (he_stride_cmd_) { rd_table_ctl_.enable_address_stride = 1; - rd_table_ctl_.stride = he_stide_; + rd_table_ctl_.stride = he_stride_; } else { // Set Stride to 3 for FPGA read/write cache hit/miss rd_table_ctl_.enable_address_stride = 1; @@ -269,9 +269,9 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL rd_table_ctl_.value = 0; - if (he_stide_cmd_) { + if (he_stride_cmd_) { rd_table_ctl_.enable_address_stride = 1; - rd_table_ctl_.stride = he_stide_; + rd_table_ctl_.stride = he_stride_; } else { // Set Stride to 3 for FPGA read/write cache hit/miss rd_table_ctl_.enable_address_stride = 1; @@ -324,9 +324,9 @@ class he_cache_cmd : public he_cmd { // Set WR_ADDR_TABLE_CTRL wr_table_ctl_.value = 0; - if (he_stide_cmd_) { + if (he_stride_cmd_) { wr_table_ctl_.enable_address_stride = 1; - wr_table_ctl_.stride = he_stide_; + wr_table_ctl_.stride = he_stride_; } else { // Set Stride to 3 for FPGA read/write cache hit/miss wr_table_ctl_.enable_address_stride = 1; @@ -388,9 +388,9 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL rd_table_ctl_.value = 0; - if (he_stide_cmd_) { + if (he_stride_cmd_) { rd_table_ctl_.enable_address_stride = 1; - rd_table_ctl_.stride = he_stide_; + rd_table_ctl_.stride = he_stride_; } else { // Set Stride to 3 for FPGA read/write cache hit/miss rd_table_ctl_.enable_address_stride = 1; @@ -464,9 +464,9 @@ class he_cache_cmd : public he_cmd { // Set WR_ADDR_TABLE_CTRL wr_table_ctl_.value = 0; - if (he_stide_cmd_) { + if (he_stride_cmd_) { wr_table_ctl_.enable_address_stride = 1; - wr_table_ctl_.stride = he_stide_; + wr_table_ctl_.stride = he_stride_; } else { // Set Stride to 3 for FPGA read/write cache hit/miss wr_table_ctl_.enable_address_stride = 1; @@ -540,9 +540,9 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL rd_table_ctl_.value = 0; - if (he_stide_cmd_) { + if (he_stride_cmd_) { rd_table_ctl_.enable_address_stride = 1; - rd_table_ctl_.stride = he_stide_; + rd_table_ctl_.stride = he_stride_; } host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); @@ -624,9 +624,9 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL wr_table_ctl_.value = 0; - if (he_stide_cmd_) { + if (he_stride_cmd_) { wr_table_ctl_.enable_address_stride = 1; - wr_table_ctl_.stride = he_stide_; + wr_table_ctl_.stride = he_stride_; } host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, wr_table_ctl_.value); @@ -705,9 +705,9 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTR rd_table_ctl_.value = 0; - if (he_stide_cmd_) { + if (he_stride_cmd_) { rd_table_ctl_.enable_address_stride = 1; - rd_table_ctl_.stride = he_stide_; + rd_table_ctl_.stride = he_stride_; } host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); @@ -778,9 +778,9 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTR wr_table_ctl_.value = 0; - if (he_stide_cmd_) { + if (he_stride_cmd_) { wr_table_ctl_.enable_address_stride = 1; - wr_table_ctl_.stride = he_stide_; + wr_table_ctl_.stride = he_stride_; } host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, rd_table_ctl_.value); @@ -833,7 +833,7 @@ class he_cache_cmd : public he_cmd { CLI::Option* opt = app->get_option_no_throw("--stride"); if (opt && opt->count() == 1) { - he_stide_cmd_ = true; + he_stride_cmd_ = true; } // reset HE cache @@ -937,11 +937,11 @@ class he_cache_cmd : public he_cmd { bool he_continuousmode_; uint32_t he_contmodetime_; uint32_t he_linerep_count_; - uint32_t he_stide_; + uint32_t he_stride_; uint32_t he_test_; bool he_test_all_; uint32_t he_dev_instance_; - bool he_stide_cmd_; + bool he_stride_cmd_; }; void he_cache_thread(uint8_t *buf_ptr, uint64_t len) { From dcaa7250a27c4bb07204b5b6a7ec68acd1f43420 Mon Sep 17 00:00:00 2001 From: anandaravuri Date: Tue, 17 Oct 2023 10:38:24 -0700 Subject: [PATCH 3/4] Fix: set stride to 3 for target fpga memory Signed-off-by: anandaravuri --- samples/cxl_host_exerciser/cxl_he_cache_cmd.h | 66 +++++++++++-------- 1 file changed, 38 insertions(+), 28 deletions(-) diff --git a/samples/cxl_host_exerciser/cxl_he_cache_cmd.h b/samples/cxl_host_exerciser/cxl_he_cache_cmd.h index 34bbcf6d7740..9b6ef4824a07 100644 --- a/samples/cxl_host_exerciser/cxl_he_cache_cmd.h +++ b/samples/cxl_host_exerciser/cxl_he_cache_cmd.h @@ -156,10 +156,13 @@ class he_cache_cmd : public he_cmd { if (he_stride_cmd_) { rd_table_ctl_.enable_address_stride = 1; rd_table_ctl_.stride = he_stride_; - } else { - // Set Stride to 3 for FPGA read/write cache hit/miss + } else if (he_target_ == HE_TARGET_FPGA) { + // Set Stride to 3 for Target FPGA Memory rd_table_ctl_.enable_address_stride = 1; rd_table_ctl_.stride = 3; + } else { + rd_table_ctl_.enable_address_stride = 1; + rd_table_ctl_.stride = he_stride_; } host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); @@ -205,10 +208,13 @@ class he_cache_cmd : public he_cmd { if (he_stride_cmd_) { rd_table_ctl_.enable_address_stride = 1; rd_table_ctl_.stride = he_stride_; - } else { - // Set Stride to 3 for FPGA read/write cache hit/miss + } else if (he_target_ == HE_TARGET_FPGA) { + // Set Stride to 3 for Target FPGA Memory rd_table_ctl_.enable_address_stride = 1; rd_table_ctl_.stride = 3; + } else { + rd_table_ctl_.enable_address_stride = 1; + rd_table_ctl_.stride = he_stride_; } host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); @@ -272,10 +278,13 @@ class he_cache_cmd : public he_cmd { if (he_stride_cmd_) { rd_table_ctl_.enable_address_stride = 1; rd_table_ctl_.stride = he_stride_; - } else { - // Set Stride to 3 for FPGA read/write cache hit/miss + } else if (he_target_ == HE_TARGET_FPGA) { + // Set Stride to 3 for Target FPGA Memory rd_table_ctl_.enable_address_stride = 1; rd_table_ctl_.stride = 3; + } else { + rd_table_ctl_.enable_address_stride = 1; + rd_table_ctl_.stride = he_stride_; } host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); @@ -327,10 +336,13 @@ class he_cache_cmd : public he_cmd { if (he_stride_cmd_) { wr_table_ctl_.enable_address_stride = 1; wr_table_ctl_.stride = he_stride_; - } else { - // Set Stride to 3 for FPGA read/write cache hit/miss + } else if (he_target_ == HE_TARGET_FPGA) { + // Set Stride to 3 for Target FPGA Memory wr_table_ctl_.enable_address_stride = 1; wr_table_ctl_.stride = 3; + } else { + wr_table_ctl_.enable_address_stride = 1; + wr_table_ctl_.stride = he_stride_; } host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, wr_table_ctl_.value); host_exe_->write64(HE_WR_NUM_LINES, FPGA_512CACHE_LINES); @@ -391,10 +403,13 @@ class he_cache_cmd : public he_cmd { if (he_stride_cmd_) { rd_table_ctl_.enable_address_stride = 1; rd_table_ctl_.stride = he_stride_; - } else { - // Set Stride to 3 for FPGA read/write cache hit/miss + } else if (he_target_ == HE_TARGET_FPGA) { + // Set Stride to 3 for Target FPGA Memory rd_table_ctl_.enable_address_stride = 1; rd_table_ctl_.stride = 3; + } else { + rd_table_ctl_.enable_address_stride = 1; + rd_table_ctl_.stride = he_stride_; } host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); @@ -467,10 +482,13 @@ class he_cache_cmd : public he_cmd { if (he_stride_cmd_) { wr_table_ctl_.enable_address_stride = 1; wr_table_ctl_.stride = he_stride_; - } else { - // Set Stride to 3 for FPGA read/write cache hit/miss + } else if (he_target_ == HE_TARGET_FPGA) { + // Set Stride to 3 for Target FPGA Memory wr_table_ctl_.enable_address_stride = 1; wr_table_ctl_.stride = 3; + } else { + wr_table_ctl_.enable_address_stride = 1; + wr_table_ctl_.stride = he_stride_; } host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, wr_table_ctl_.value); @@ -540,10 +558,8 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL rd_table_ctl_.value = 0; - if (he_stride_cmd_) { - rd_table_ctl_.enable_address_stride = 1; - rd_table_ctl_.stride = he_stride_; - } + rd_table_ctl_.enable_address_stride = 1; + rd_table_ctl_.stride = he_stride_; host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); // Allocate DSM buffer @@ -624,10 +640,8 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL wr_table_ctl_.value = 0; - if (he_stride_cmd_) { - wr_table_ctl_.enable_address_stride = 1; - wr_table_ctl_.stride = he_stride_; - } + wr_table_ctl_.enable_address_stride = 1; + wr_table_ctl_.stride = he_stride_; host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, wr_table_ctl_.value); // Allocate DSM buffer @@ -705,10 +719,8 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTR rd_table_ctl_.value = 0; - if (he_stride_cmd_) { - rd_table_ctl_.enable_address_stride = 1; - rd_table_ctl_.stride = he_stride_; - } + rd_table_ctl_.enable_address_stride = 1; + rd_table_ctl_.stride = he_stride_; host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); // Allocate DSM buffer @@ -778,10 +790,8 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTR wr_table_ctl_.value = 0; - if (he_stride_cmd_) { - wr_table_ctl_.enable_address_stride = 1; - wr_table_ctl_.stride = he_stride_; - } + wr_table_ctl_.enable_address_stride = 1; + wr_table_ctl_.stride = he_stride_; host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, rd_table_ctl_.value); // Allocate DSM buffer From 2c04125a8fe95abb76dc0a83cb360f96cbaac8ea Mon Sep 17 00:00:00 2001 From: anandaravuri Date: Tue, 17 Oct 2023 12:15:19 -0700 Subject: [PATCH 4/4] fix: change he-cache output message Signed-off-by: anandaravuri --- samples/cxl_host_exerciser/cxl_he_cache_cmd.h | 2 +- samples/cxl_host_exerciser/cxl_he_cmd.h | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/samples/cxl_host_exerciser/cxl_he_cache_cmd.h b/samples/cxl_host_exerciser/cxl_he_cache_cmd.h index 9b6ef4824a07..4e478bb678de 100644 --- a/samples/cxl_host_exerciser/cxl_he_cache_cmd.h +++ b/samples/cxl_host_exerciser/cxl_he_cache_cmd.h @@ -95,7 +95,7 @@ class he_cache_cmd : public he_cmd { ->default_val("host"); app->add_option("--bias", he_bias_, - "host exerciser run on host or device") + "CXL IP memory access Bias mode: host or device") ->transform(CLI::CheckedTransformer(he_bias)) ->default_val("host"); diff --git a/samples/cxl_host_exerciser/cxl_he_cmd.h b/samples/cxl_host_exerciser/cxl_he_cmd.h index ba083c1e6308..366cffe07c09 100644 --- a/samples/cxl_host_exerciser/cxl_he_cmd.h +++ b/samples/cxl_host_exerciser/cxl_he_cmd.h @@ -251,8 +251,7 @@ class he_cmd : public test_command { if (he_bias_ == HOSTMEM_BIAS) { he_ctl_.bias_support = HOSTMEM_BIAS; } else { - cerr << "Invalid configuration:Target memory host and bias device" - << endl; + cerr << "Wrong BIAS mode for specified target memory type" << endl; return false; } } else {