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Commits on May 31, 2023

• fix typo in ifndef

  hansfbaier

  committedMay 31, 2023
  e85d03d

• synchronize SPI inputs to sys_clk. This makes MISO 1 bit late, but we compensate for that in Main_MiSTeX

  hansfbaier

  committedMay 31, 2023
  68e1718

Commits on May 24, 2023

• fix DISABLE_VGA

  hansfbaier

  committedMay 24, 2023
  a3ed2ce

• put screen_rotate at 0x6000000 (byte addressed)

  hansfbaier

  committedMay 24, 2023
  c559008

Commits on May 23, 2023

• fix comment

  hansfbaier

  committedMay 23, 2023
  7fb6e07

• actually connect FB DDRAM port to LiteDRAM, and route its clock out

  hansfbaier

  committedMay 23, 2023
  03f0d82

Commits on May 15, 2023

• Add MiSTeX HDMI conditionals

  hansfbaier

  committedMay 15, 2023
  d24b75b

Commits on May 1, 2023

• fix dead screen if DISABLE_VGA is selected, fix CRG_AUDIO_CLK

  hansfbaier

  committedMay 1, 2023
  7b5aee1

• make audio pll verilog compatible with non-cyclone v devices

  hansfbaier

  committedMay 1, 2023
  abad2d5

Commits on Apr 29, 2023

• sys_top, audio_out: add options to skip shadowmask, IIR filter, fix DISABLE_VGA

  hansfbaier

  committedApr 29, 2023
  b154188

Commits on Apr 26, 2023

• add HDMI PLL for Xilinx

  hansfbaier

  committedApr 26, 2023
  2340b0f

• parameterize ascal RAMBASE

  hansfbaier

  committedApr 26, 2023
  ffade41

• make HDMI compile with Xilinx

  hansfbaier

  committedApr 26, 2023
  c5bd7ae

• fix verilog syntax error

  hansfbaier

  committedApr 26, 2023
  ddfbf22

Commits on Apr 15, 2023

• properly implement NO_SCANDOUBLER option

  hansfbaier

  committedApr 15, 2023
  537c808

Commits on Apr 13, 2023

• fix device family in reconfig PLL

  hansfbaier

  committedApr 13, 2023
  dfa6c74

• add a number of defines to disable parts to save resources

  hansfbaier

  committedApr 13, 2023
  a4f4118

Commits on Apr 11, 2023

• pll_0002.v: tidy

  hansfbaier

  committedApr 11, 2023
  487b196

• got DDR3 with ascal working on terasic DECA

  hansfbaier

  committedApr 11, 2023
  665bd9a

Commits on Apr 7, 2023

• actually use hardware HDMI initialization

  hansfbaier

  committedApr 7, 2023
  1da80e3

• bring back hardware HDMI I2C init, for the terasic DECA board

  hansfbaier

  committedApr 7, 2023
  87363d2

• tidy PLLs and add noin-cyclonev altplls for DECA

  hansfbaier

  committedApr 7, 2023
  f78a526

• fix input clock period in top_crg.v

  hansfbaier

  committedApr 7, 2023
  398833c

Commits on Mar 28, 2023

• prepare for DDR3

  hansfbaier

  committedMar 28, 2023
  2bbc00e

Commits on Mar 22, 2023

• fix build_id include

  hansfbaier

  committedMar 22, 2023
  b144c09

• update .gitignore

  hansfbaier

  committedMar 22, 2023
  325aa56

• tidy pll_audio

  hansfbaier

  committedMar 22, 2023
  a9b6734

• Merge branch 'MiSTer-devel:master' into master

  hansfbaier

  committedMar 22, 2023
  cf2f178

• make HPS debug work again, make it run on Artix7

  hansfbaier

  committedMar 22, 2023
  4ec179c

Commits on Mar 21, 2023

• make it compile on Xilinx

  hansfbaier

  committedMar 21, 2023
  b65d293

Commits on Mar 20, 2023

• first attempt at xilinx port

  hansfbaier

  committedMar 20, 2023
  39c615b

Commits on Mar 7, 2023

• Add v option to CONF_STR.

  sorgelig

  committedMar 7, 2023
  f83fb47

• add MiSTeX.yaml

  hansfbaier

  committedMar 7, 2023
  8cf0ce1

• add mistex.yaml

  hansfbaier

  committedMar 7, 2023
  9ab3dba

• remove cruft

  hansfbaier

  committedMar 7, 2023
  9ee619d

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