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trace-hw_ppc.c
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trace-hw_ppc.c
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/* This file is autogenerated by tracetool, do not edit. */
#include "qemu/osdep.h"
#include "qemu/module.h"
#include "trace-hw_ppc.h"
uint16_t _TRACE_SPAPR_PCI_MSI_DSTATE;
uint16_t _TRACE_SPAPR_PCI_MSI_SETUP_DSTATE;
uint16_t _TRACE_SPAPR_PCI_RTAS_IBM_CHANGE_MSI_DSTATE;
uint16_t _TRACE_SPAPR_PCI_RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER_DSTATE;
uint16_t _TRACE_SPAPR_PCI_MSI_WRITE_DSTATE;
uint16_t _TRACE_SPAPR_PCI_LSI_SET_DSTATE;
uint16_t _TRACE_SPAPR_PCI_MSI_RETRY_DSTATE;
uint16_t _TRACE_SPAPR_CAS_CONTINUE_DSTATE;
uint16_t _TRACE_SPAPR_CAS_PVR_DSTATE;
uint16_t _TRACE_SPAPR_H_RESIZE_HPT_PREPARE_DSTATE;
uint16_t _TRACE_SPAPR_H_RESIZE_HPT_COMMIT_DSTATE;
uint16_t _TRACE_SPAPR_UPDATE_DT_DSTATE;
uint16_t _TRACE_SPAPR_UPDATE_DT_FAILED_SIZE_DSTATE;
uint16_t _TRACE_SPAPR_UPDATE_DT_FAILED_CHECK_DSTATE;
uint16_t _TRACE_SPAPR_H_TPM_COMM_DSTATE;
uint16_t _TRACE_SPAPR_TPM_EXECUTE_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_PUT_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_GET_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_INDIRECT_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_STUFF_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_PCI_PUT_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_PCI_GET_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_PCI_INDIRECT_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_PCI_STUFF_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_XLATE_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_NEW_TABLE_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_PRE_SAVE_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_POST_LOAD_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_DDW_QUERY_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_DDW_CREATE_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_DDW_REMOVE_DSTATE;
uint16_t _TRACE_SPAPR_IOMMU_DDW_RESET_DSTATE;
uint16_t _TRACE_SPAPR_DRC_SET_ISOLATION_STATE_DSTATE;
uint16_t _TRACE_SPAPR_DRC_SET_ISOLATION_STATE_FINALIZING_DSTATE;
uint16_t _TRACE_SPAPR_DRC_SET_DR_INDICATOR_DSTATE;
uint16_t _TRACE_SPAPR_DRC_SET_ALLOCATION_STATE_DSTATE;
uint16_t _TRACE_SPAPR_DRC_SET_ALLOCATION_STATE_FINALIZING_DSTATE;
uint16_t _TRACE_SPAPR_DRC_SET_CONFIGURED_DSTATE;
uint16_t _TRACE_SPAPR_DRC_ATTACH_DSTATE;
uint16_t _TRACE_SPAPR_DRC_UNPLUG_REQUEST_DSTATE;
uint16_t _TRACE_SPAPR_DRC_AWAITING_QUIESCE_DSTATE;
uint16_t _TRACE_SPAPR_DRC_RESET_DSTATE;
uint16_t _TRACE_SPAPR_DRC_REALIZE_DSTATE;
uint16_t _TRACE_SPAPR_DRC_REALIZE_CHILD_DSTATE;
uint16_t _TRACE_SPAPR_DRC_REALIZE_COMPLETE_DSTATE;
uint16_t _TRACE_SPAPR_DRC_UNREALIZE_DSTATE;
uint16_t _TRACE_SPAPR_OVEC_PARSE_VECTOR_DSTATE;
uint16_t _TRACE_SPAPR_OVEC_POPULATE_DT_DSTATE;
uint16_t _TRACE_SPAPR_RTAS_GET_SENSOR_STATE_NOT_SUPPORTED_DSTATE;
uint16_t _TRACE_SPAPR_RTAS_GET_SENSOR_STATE_INVALID_DSTATE;
uint16_t _TRACE_SPAPR_RTAS_IBM_CONFIGURE_CONNECTOR_INVALID_DSTATE;
uint16_t _TRACE_SPAPR_VIO_H_REG_CRQ_DSTATE;
uint16_t _TRACE_SPAPR_VIO_FREE_CRQ_DSTATE;
uint16_t _TRACE_VOF_ERROR_STR_TRUNCATED_DSTATE;
uint16_t _TRACE_VOF_ERROR_PARAM_DSTATE;
uint16_t _TRACE_VOF_ERROR_UNKNOWN_SERVICE_DSTATE;
uint16_t _TRACE_VOF_ERROR_UNKNOWN_METHOD_DSTATE;
uint16_t _TRACE_VOF_ERROR_UNKNOWN_IHANDLE_CLOSE_DSTATE;
uint16_t _TRACE_VOF_ERROR_UNKNOWN_PATH_DSTATE;
uint16_t _TRACE_VOF_ERROR_WRITE_DSTATE;
uint16_t _TRACE_VOF_FINDDEVICE_DSTATE;
uint16_t _TRACE_VOF_CLAIM_DSTATE;
uint16_t _TRACE_VOF_RELEASE_DSTATE;
uint16_t _TRACE_VOF_METHOD_DSTATE;
uint16_t _TRACE_VOF_GETPROP_DSTATE;
uint16_t _TRACE_VOF_GETPROPLEN_DSTATE;
uint16_t _TRACE_VOF_SETPROP_DSTATE;
uint16_t _TRACE_VOF_OPEN_DSTATE;
uint16_t _TRACE_VOF_INTERPRET_DSTATE;
uint16_t _TRACE_VOF_PACKAGE_TO_PATH_DSTATE;
uint16_t _TRACE_VOF_INSTANCE_TO_PATH_DSTATE;
uint16_t _TRACE_VOF_INSTANCE_TO_PACKAGE_DSTATE;
uint16_t _TRACE_VOF_WRITE_DSTATE;
uint16_t _TRACE_VOF_AVAIL_DSTATE;
uint16_t _TRACE_VOF_CLAIMED_DSTATE;
uint16_t _TRACE_PPC_TB_ADJUST_DSTATE;
uint16_t _TRACE_PPC_TB_LOAD_DSTATE;
uint16_t _TRACE_PPC_TB_STORE_DSTATE;
uint16_t _TRACE_PPC_DECR_LOAD_DSTATE;
uint16_t _TRACE_PPC_DECR_EXCP_DSTATE;
uint16_t _TRACE_PPC_DECR_STORE_DSTATE;
uint16_t _TRACE_PPC4XX_FIT_DSTATE;
uint16_t _TRACE_PPC4XX_PIT_STOP_DSTATE;
uint16_t _TRACE_PPC4XX_PIT_START_DSTATE;
uint16_t _TRACE_PPC4XX_PIT_DSTATE;
uint16_t _TRACE_PPC4XX_WDT_DSTATE;
uint16_t _TRACE_PPC40X_STORE_PIT_DSTATE;
uint16_t _TRACE_PPC40X_STORE_TCR_DSTATE;
uint16_t _TRACE_PPC40X_STORE_TSR_DSTATE;
uint16_t _TRACE_PPC40X_SET_TB_CLK_DSTATE;
uint16_t _TRACE_PPC40X_TIMERS_INIT_DSTATE;
uint16_t _TRACE_PPC_IRQ_SET_DSTATE;
uint16_t _TRACE_PPC_IRQ_SET_EXIT_DSTATE;
uint16_t _TRACE_PPC_IRQ_SET_STATE_DSTATE;
uint16_t _TRACE_PPC_IRQ_RESET_DSTATE;
uint16_t _TRACE_PPC_IRQ_CPU_DSTATE;
uint16_t _TRACE_PPC_DCR_READ_DSTATE;
uint16_t _TRACE_PPC_DCR_WRITE_DSTATE;
uint16_t _TRACE_PREP_SYSTEMIO_READ_DSTATE;
uint16_t _TRACE_PREP_SYSTEMIO_WRITE_DSTATE;
uint16_t _TRACE_RS6000MC_ID_READ_DSTATE;
uint16_t _TRACE_RS6000MC_PRESENCE_READ_DSTATE;
uint16_t _TRACE_RS6000MC_SIZE_READ_DSTATE;
uint16_t _TRACE_RS6000MC_SIZE_WRITE_DSTATE;
uint16_t _TRACE_RS6000MC_PARITY_READ_DSTATE;
uint16_t _TRACE_PPC4XX_PCI_MAP_IRQ_DSTATE;
uint16_t _TRACE_PPC4XX_PCI_SET_IRQ_DSTATE;
uint16_t _TRACE_PPC440_PCIX_MAP_IRQ_DSTATE;
uint16_t _TRACE_PPC440_PCIX_SET_IRQ_DSTATE;
uint16_t _TRACE_PPC440_PCIX_UPDATE_PIM_DSTATE;
uint16_t _TRACE_PPC440_PCIX_UPDATE_POM_DSTATE;
uint16_t _TRACE_PPC440_PCIX_REG_READ_DSTATE;
uint16_t _TRACE_PPC440_PCIX_REG_WRITE_DSTATE;
uint16_t _TRACE_OPBA_READB_DSTATE;
uint16_t _TRACE_OPBA_WRITEB_DSTATE;
uint16_t _TRACE_OPBA_INIT_DSTATE;
uint16_t _TRACE_PPC405_GPIO_READ_DSTATE;
uint16_t _TRACE_PPC405_GPIO_WRITE_DSTATE;
uint16_t _TRACE_PPC405_GPIO_INIT_DSTATE;
uint16_t _TRACE_OCM_UPDATE_MAPPINGS_DSTATE;
uint16_t _TRACE_OCM_MAP_DSTATE;
uint16_t _TRACE_OCM_UNMAP_DSTATE;
uint16_t _TRACE_PPC4XX_GPT_READ_DSTATE;
uint16_t _TRACE_PPC4XX_GPT_WRITE_DSTATE;
uint16_t _TRACE_PPC4XX_GPT_INIT_DSTATE;
uint16_t _TRACE_PPC405EP_CLOCKS_COMPUTE_DSTATE;
uint16_t _TRACE_PPC405EP_CLOCKS_SETUP_DSTATE;
uint16_t _TRACE_PPC4XX_SDRAM_ENABLE_DSTATE;
uint16_t _TRACE_PPC4XX_SDRAM_UNMAP_DSTATE;
uint16_t _TRACE_PPC4XX_SDRAM_MAP_DSTATE;
TraceEvent _TRACE_SPAPR_PCI_MSI_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_pci_msi",
.sstate = TRACE_SPAPR_PCI_MSI_ENABLED,
.dstate = &_TRACE_SPAPR_PCI_MSI_DSTATE
};
TraceEvent _TRACE_SPAPR_PCI_MSI_SETUP_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_pci_msi_setup",
.sstate = TRACE_SPAPR_PCI_MSI_SETUP_ENABLED,
.dstate = &_TRACE_SPAPR_PCI_MSI_SETUP_DSTATE
};
TraceEvent _TRACE_SPAPR_PCI_RTAS_IBM_CHANGE_MSI_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_pci_rtas_ibm_change_msi",
.sstate = TRACE_SPAPR_PCI_RTAS_IBM_CHANGE_MSI_ENABLED,
.dstate = &_TRACE_SPAPR_PCI_RTAS_IBM_CHANGE_MSI_DSTATE
};
TraceEvent _TRACE_SPAPR_PCI_RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_pci_rtas_ibm_query_interrupt_source_number",
.sstate = TRACE_SPAPR_PCI_RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER_ENABLED,
.dstate = &_TRACE_SPAPR_PCI_RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER_DSTATE
};
TraceEvent _TRACE_SPAPR_PCI_MSI_WRITE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_pci_msi_write",
.sstate = TRACE_SPAPR_PCI_MSI_WRITE_ENABLED,
.dstate = &_TRACE_SPAPR_PCI_MSI_WRITE_DSTATE
};
TraceEvent _TRACE_SPAPR_PCI_LSI_SET_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_pci_lsi_set",
.sstate = TRACE_SPAPR_PCI_LSI_SET_ENABLED,
.dstate = &_TRACE_SPAPR_PCI_LSI_SET_DSTATE
};
TraceEvent _TRACE_SPAPR_PCI_MSI_RETRY_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_pci_msi_retry",
.sstate = TRACE_SPAPR_PCI_MSI_RETRY_ENABLED,
.dstate = &_TRACE_SPAPR_PCI_MSI_RETRY_DSTATE
};
TraceEvent _TRACE_SPAPR_CAS_CONTINUE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_cas_continue",
.sstate = TRACE_SPAPR_CAS_CONTINUE_ENABLED,
.dstate = &_TRACE_SPAPR_CAS_CONTINUE_DSTATE
};
TraceEvent _TRACE_SPAPR_CAS_PVR_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_cas_pvr",
.sstate = TRACE_SPAPR_CAS_PVR_ENABLED,
.dstate = &_TRACE_SPAPR_CAS_PVR_DSTATE
};
TraceEvent _TRACE_SPAPR_H_RESIZE_HPT_PREPARE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_h_resize_hpt_prepare",
.sstate = TRACE_SPAPR_H_RESIZE_HPT_PREPARE_ENABLED,
.dstate = &_TRACE_SPAPR_H_RESIZE_HPT_PREPARE_DSTATE
};
TraceEvent _TRACE_SPAPR_H_RESIZE_HPT_COMMIT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_h_resize_hpt_commit",
.sstate = TRACE_SPAPR_H_RESIZE_HPT_COMMIT_ENABLED,
.dstate = &_TRACE_SPAPR_H_RESIZE_HPT_COMMIT_DSTATE
};
TraceEvent _TRACE_SPAPR_UPDATE_DT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_update_dt",
.sstate = TRACE_SPAPR_UPDATE_DT_ENABLED,
.dstate = &_TRACE_SPAPR_UPDATE_DT_DSTATE
};
TraceEvent _TRACE_SPAPR_UPDATE_DT_FAILED_SIZE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_update_dt_failed_size",
.sstate = TRACE_SPAPR_UPDATE_DT_FAILED_SIZE_ENABLED,
.dstate = &_TRACE_SPAPR_UPDATE_DT_FAILED_SIZE_DSTATE
};
TraceEvent _TRACE_SPAPR_UPDATE_DT_FAILED_CHECK_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_update_dt_failed_check",
.sstate = TRACE_SPAPR_UPDATE_DT_FAILED_CHECK_ENABLED,
.dstate = &_TRACE_SPAPR_UPDATE_DT_FAILED_CHECK_DSTATE
};
TraceEvent _TRACE_SPAPR_H_TPM_COMM_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_h_tpm_comm",
.sstate = TRACE_SPAPR_H_TPM_COMM_ENABLED,
.dstate = &_TRACE_SPAPR_H_TPM_COMM_DSTATE
};
TraceEvent _TRACE_SPAPR_TPM_EXECUTE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_tpm_execute",
.sstate = TRACE_SPAPR_TPM_EXECUTE_ENABLED,
.dstate = &_TRACE_SPAPR_TPM_EXECUTE_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_PUT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_put",
.sstate = TRACE_SPAPR_IOMMU_PUT_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_PUT_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_GET_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_get",
.sstate = TRACE_SPAPR_IOMMU_GET_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_GET_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_INDIRECT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_indirect",
.sstate = TRACE_SPAPR_IOMMU_INDIRECT_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_INDIRECT_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_STUFF_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_stuff",
.sstate = TRACE_SPAPR_IOMMU_STUFF_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_STUFF_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_PCI_PUT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_pci_put",
.sstate = TRACE_SPAPR_IOMMU_PCI_PUT_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_PCI_PUT_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_PCI_GET_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_pci_get",
.sstate = TRACE_SPAPR_IOMMU_PCI_GET_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_PCI_GET_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_PCI_INDIRECT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_pci_indirect",
.sstate = TRACE_SPAPR_IOMMU_PCI_INDIRECT_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_PCI_INDIRECT_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_PCI_STUFF_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_pci_stuff",
.sstate = TRACE_SPAPR_IOMMU_PCI_STUFF_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_PCI_STUFF_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_XLATE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_xlate",
.sstate = TRACE_SPAPR_IOMMU_XLATE_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_XLATE_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_NEW_TABLE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_new_table",
.sstate = TRACE_SPAPR_IOMMU_NEW_TABLE_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_NEW_TABLE_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_PRE_SAVE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_pre_save",
.sstate = TRACE_SPAPR_IOMMU_PRE_SAVE_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_PRE_SAVE_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_POST_LOAD_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_post_load",
.sstate = TRACE_SPAPR_IOMMU_POST_LOAD_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_POST_LOAD_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_DDW_QUERY_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_ddw_query",
.sstate = TRACE_SPAPR_IOMMU_DDW_QUERY_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_DDW_QUERY_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_DDW_CREATE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_ddw_create",
.sstate = TRACE_SPAPR_IOMMU_DDW_CREATE_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_DDW_CREATE_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_DDW_REMOVE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_ddw_remove",
.sstate = TRACE_SPAPR_IOMMU_DDW_REMOVE_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_DDW_REMOVE_DSTATE
};
TraceEvent _TRACE_SPAPR_IOMMU_DDW_RESET_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_iommu_ddw_reset",
.sstate = TRACE_SPAPR_IOMMU_DDW_RESET_ENABLED,
.dstate = &_TRACE_SPAPR_IOMMU_DDW_RESET_DSTATE
};
TraceEvent _TRACE_SPAPR_DRC_SET_ISOLATION_STATE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_drc_set_isolation_state",
.sstate = TRACE_SPAPR_DRC_SET_ISOLATION_STATE_ENABLED,
.dstate = &_TRACE_SPAPR_DRC_SET_ISOLATION_STATE_DSTATE
};
TraceEvent _TRACE_SPAPR_DRC_SET_ISOLATION_STATE_FINALIZING_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_drc_set_isolation_state_finalizing",
.sstate = TRACE_SPAPR_DRC_SET_ISOLATION_STATE_FINALIZING_ENABLED,
.dstate = &_TRACE_SPAPR_DRC_SET_ISOLATION_STATE_FINALIZING_DSTATE
};
TraceEvent _TRACE_SPAPR_DRC_SET_DR_INDICATOR_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_drc_set_dr_indicator",
.sstate = TRACE_SPAPR_DRC_SET_DR_INDICATOR_ENABLED,
.dstate = &_TRACE_SPAPR_DRC_SET_DR_INDICATOR_DSTATE
};
TraceEvent _TRACE_SPAPR_DRC_SET_ALLOCATION_STATE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_drc_set_allocation_state",
.sstate = TRACE_SPAPR_DRC_SET_ALLOCATION_STATE_ENABLED,
.dstate = &_TRACE_SPAPR_DRC_SET_ALLOCATION_STATE_DSTATE
};
TraceEvent _TRACE_SPAPR_DRC_SET_ALLOCATION_STATE_FINALIZING_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_drc_set_allocation_state_finalizing",
.sstate = TRACE_SPAPR_DRC_SET_ALLOCATION_STATE_FINALIZING_ENABLED,
.dstate = &_TRACE_SPAPR_DRC_SET_ALLOCATION_STATE_FINALIZING_DSTATE
};
TraceEvent _TRACE_SPAPR_DRC_SET_CONFIGURED_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_drc_set_configured",
.sstate = TRACE_SPAPR_DRC_SET_CONFIGURED_ENABLED,
.dstate = &_TRACE_SPAPR_DRC_SET_CONFIGURED_DSTATE
};
TraceEvent _TRACE_SPAPR_DRC_ATTACH_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_drc_attach",
.sstate = TRACE_SPAPR_DRC_ATTACH_ENABLED,
.dstate = &_TRACE_SPAPR_DRC_ATTACH_DSTATE
};
TraceEvent _TRACE_SPAPR_DRC_UNPLUG_REQUEST_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_drc_unplug_request",
.sstate = TRACE_SPAPR_DRC_UNPLUG_REQUEST_ENABLED,
.dstate = &_TRACE_SPAPR_DRC_UNPLUG_REQUEST_DSTATE
};
TraceEvent _TRACE_SPAPR_DRC_AWAITING_QUIESCE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_drc_awaiting_quiesce",
.sstate = TRACE_SPAPR_DRC_AWAITING_QUIESCE_ENABLED,
.dstate = &_TRACE_SPAPR_DRC_AWAITING_QUIESCE_DSTATE
};
TraceEvent _TRACE_SPAPR_DRC_RESET_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_drc_reset",
.sstate = TRACE_SPAPR_DRC_RESET_ENABLED,
.dstate = &_TRACE_SPAPR_DRC_RESET_DSTATE
};
TraceEvent _TRACE_SPAPR_DRC_REALIZE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_drc_realize",
.sstate = TRACE_SPAPR_DRC_REALIZE_ENABLED,
.dstate = &_TRACE_SPAPR_DRC_REALIZE_DSTATE
};
TraceEvent _TRACE_SPAPR_DRC_REALIZE_CHILD_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_drc_realize_child",
.sstate = TRACE_SPAPR_DRC_REALIZE_CHILD_ENABLED,
.dstate = &_TRACE_SPAPR_DRC_REALIZE_CHILD_DSTATE
};
TraceEvent _TRACE_SPAPR_DRC_REALIZE_COMPLETE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_drc_realize_complete",
.sstate = TRACE_SPAPR_DRC_REALIZE_COMPLETE_ENABLED,
.dstate = &_TRACE_SPAPR_DRC_REALIZE_COMPLETE_DSTATE
};
TraceEvent _TRACE_SPAPR_DRC_UNREALIZE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_drc_unrealize",
.sstate = TRACE_SPAPR_DRC_UNREALIZE_ENABLED,
.dstate = &_TRACE_SPAPR_DRC_UNREALIZE_DSTATE
};
TraceEvent _TRACE_SPAPR_OVEC_PARSE_VECTOR_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_ovec_parse_vector",
.sstate = TRACE_SPAPR_OVEC_PARSE_VECTOR_ENABLED,
.dstate = &_TRACE_SPAPR_OVEC_PARSE_VECTOR_DSTATE
};
TraceEvent _TRACE_SPAPR_OVEC_POPULATE_DT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_ovec_populate_dt",
.sstate = TRACE_SPAPR_OVEC_POPULATE_DT_ENABLED,
.dstate = &_TRACE_SPAPR_OVEC_POPULATE_DT_DSTATE
};
TraceEvent _TRACE_SPAPR_RTAS_GET_SENSOR_STATE_NOT_SUPPORTED_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_rtas_get_sensor_state_not_supported",
.sstate = TRACE_SPAPR_RTAS_GET_SENSOR_STATE_NOT_SUPPORTED_ENABLED,
.dstate = &_TRACE_SPAPR_RTAS_GET_SENSOR_STATE_NOT_SUPPORTED_DSTATE
};
TraceEvent _TRACE_SPAPR_RTAS_GET_SENSOR_STATE_INVALID_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_rtas_get_sensor_state_invalid",
.sstate = TRACE_SPAPR_RTAS_GET_SENSOR_STATE_INVALID_ENABLED,
.dstate = &_TRACE_SPAPR_RTAS_GET_SENSOR_STATE_INVALID_DSTATE
};
TraceEvent _TRACE_SPAPR_RTAS_IBM_CONFIGURE_CONNECTOR_INVALID_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_rtas_ibm_configure_connector_invalid",
.sstate = TRACE_SPAPR_RTAS_IBM_CONFIGURE_CONNECTOR_INVALID_ENABLED,
.dstate = &_TRACE_SPAPR_RTAS_IBM_CONFIGURE_CONNECTOR_INVALID_DSTATE
};
TraceEvent _TRACE_SPAPR_VIO_H_REG_CRQ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_vio_h_reg_crq",
.sstate = TRACE_SPAPR_VIO_H_REG_CRQ_ENABLED,
.dstate = &_TRACE_SPAPR_VIO_H_REG_CRQ_DSTATE
};
TraceEvent _TRACE_SPAPR_VIO_FREE_CRQ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "spapr_vio_free_crq",
.sstate = TRACE_SPAPR_VIO_FREE_CRQ_ENABLED,
.dstate = &_TRACE_SPAPR_VIO_FREE_CRQ_DSTATE
};
TraceEvent _TRACE_VOF_ERROR_STR_TRUNCATED_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_error_str_truncated",
.sstate = TRACE_VOF_ERROR_STR_TRUNCATED_ENABLED,
.dstate = &_TRACE_VOF_ERROR_STR_TRUNCATED_DSTATE
};
TraceEvent _TRACE_VOF_ERROR_PARAM_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_error_param",
.sstate = TRACE_VOF_ERROR_PARAM_ENABLED,
.dstate = &_TRACE_VOF_ERROR_PARAM_DSTATE
};
TraceEvent _TRACE_VOF_ERROR_UNKNOWN_SERVICE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_error_unknown_service",
.sstate = TRACE_VOF_ERROR_UNKNOWN_SERVICE_ENABLED,
.dstate = &_TRACE_VOF_ERROR_UNKNOWN_SERVICE_DSTATE
};
TraceEvent _TRACE_VOF_ERROR_UNKNOWN_METHOD_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_error_unknown_method",
.sstate = TRACE_VOF_ERROR_UNKNOWN_METHOD_ENABLED,
.dstate = &_TRACE_VOF_ERROR_UNKNOWN_METHOD_DSTATE
};
TraceEvent _TRACE_VOF_ERROR_UNKNOWN_IHANDLE_CLOSE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_error_unknown_ihandle_close",
.sstate = TRACE_VOF_ERROR_UNKNOWN_IHANDLE_CLOSE_ENABLED,
.dstate = &_TRACE_VOF_ERROR_UNKNOWN_IHANDLE_CLOSE_DSTATE
};
TraceEvent _TRACE_VOF_ERROR_UNKNOWN_PATH_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_error_unknown_path",
.sstate = TRACE_VOF_ERROR_UNKNOWN_PATH_ENABLED,
.dstate = &_TRACE_VOF_ERROR_UNKNOWN_PATH_DSTATE
};
TraceEvent _TRACE_VOF_ERROR_WRITE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_error_write",
.sstate = TRACE_VOF_ERROR_WRITE_ENABLED,
.dstate = &_TRACE_VOF_ERROR_WRITE_DSTATE
};
TraceEvent _TRACE_VOF_FINDDEVICE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_finddevice",
.sstate = TRACE_VOF_FINDDEVICE_ENABLED,
.dstate = &_TRACE_VOF_FINDDEVICE_DSTATE
};
TraceEvent _TRACE_VOF_CLAIM_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_claim",
.sstate = TRACE_VOF_CLAIM_ENABLED,
.dstate = &_TRACE_VOF_CLAIM_DSTATE
};
TraceEvent _TRACE_VOF_RELEASE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_release",
.sstate = TRACE_VOF_RELEASE_ENABLED,
.dstate = &_TRACE_VOF_RELEASE_DSTATE
};
TraceEvent _TRACE_VOF_METHOD_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_method",
.sstate = TRACE_VOF_METHOD_ENABLED,
.dstate = &_TRACE_VOF_METHOD_DSTATE
};
TraceEvent _TRACE_VOF_GETPROP_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_getprop",
.sstate = TRACE_VOF_GETPROP_ENABLED,
.dstate = &_TRACE_VOF_GETPROP_DSTATE
};
TraceEvent _TRACE_VOF_GETPROPLEN_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_getproplen",
.sstate = TRACE_VOF_GETPROPLEN_ENABLED,
.dstate = &_TRACE_VOF_GETPROPLEN_DSTATE
};
TraceEvent _TRACE_VOF_SETPROP_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_setprop",
.sstate = TRACE_VOF_SETPROP_ENABLED,
.dstate = &_TRACE_VOF_SETPROP_DSTATE
};
TraceEvent _TRACE_VOF_OPEN_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_open",
.sstate = TRACE_VOF_OPEN_ENABLED,
.dstate = &_TRACE_VOF_OPEN_DSTATE
};
TraceEvent _TRACE_VOF_INTERPRET_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_interpret",
.sstate = TRACE_VOF_INTERPRET_ENABLED,
.dstate = &_TRACE_VOF_INTERPRET_DSTATE
};
TraceEvent _TRACE_VOF_PACKAGE_TO_PATH_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_package_to_path",
.sstate = TRACE_VOF_PACKAGE_TO_PATH_ENABLED,
.dstate = &_TRACE_VOF_PACKAGE_TO_PATH_DSTATE
};
TraceEvent _TRACE_VOF_INSTANCE_TO_PATH_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_instance_to_path",
.sstate = TRACE_VOF_INSTANCE_TO_PATH_ENABLED,
.dstate = &_TRACE_VOF_INSTANCE_TO_PATH_DSTATE
};
TraceEvent _TRACE_VOF_INSTANCE_TO_PACKAGE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_instance_to_package",
.sstate = TRACE_VOF_INSTANCE_TO_PACKAGE_ENABLED,
.dstate = &_TRACE_VOF_INSTANCE_TO_PACKAGE_DSTATE
};
TraceEvent _TRACE_VOF_WRITE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_write",
.sstate = TRACE_VOF_WRITE_ENABLED,
.dstate = &_TRACE_VOF_WRITE_DSTATE
};
TraceEvent _TRACE_VOF_AVAIL_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_avail",
.sstate = TRACE_VOF_AVAIL_ENABLED,
.dstate = &_TRACE_VOF_AVAIL_DSTATE
};
TraceEvent _TRACE_VOF_CLAIMED_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "vof_claimed",
.sstate = TRACE_VOF_CLAIMED_ENABLED,
.dstate = &_TRACE_VOF_CLAIMED_DSTATE
};
TraceEvent _TRACE_PPC_TB_ADJUST_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc_tb_adjust",
.sstate = TRACE_PPC_TB_ADJUST_ENABLED,
.dstate = &_TRACE_PPC_TB_ADJUST_DSTATE
};
TraceEvent _TRACE_PPC_TB_LOAD_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc_tb_load",
.sstate = TRACE_PPC_TB_LOAD_ENABLED,
.dstate = &_TRACE_PPC_TB_LOAD_DSTATE
};
TraceEvent _TRACE_PPC_TB_STORE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc_tb_store",
.sstate = TRACE_PPC_TB_STORE_ENABLED,
.dstate = &_TRACE_PPC_TB_STORE_DSTATE
};
TraceEvent _TRACE_PPC_DECR_LOAD_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc_decr_load",
.sstate = TRACE_PPC_DECR_LOAD_ENABLED,
.dstate = &_TRACE_PPC_DECR_LOAD_DSTATE
};
TraceEvent _TRACE_PPC_DECR_EXCP_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc_decr_excp",
.sstate = TRACE_PPC_DECR_EXCP_ENABLED,
.dstate = &_TRACE_PPC_DECR_EXCP_DSTATE
};
TraceEvent _TRACE_PPC_DECR_STORE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc_decr_store",
.sstate = TRACE_PPC_DECR_STORE_ENABLED,
.dstate = &_TRACE_PPC_DECR_STORE_DSTATE
};
TraceEvent _TRACE_PPC4XX_FIT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc4xx_fit",
.sstate = TRACE_PPC4XX_FIT_ENABLED,
.dstate = &_TRACE_PPC4XX_FIT_DSTATE
};
TraceEvent _TRACE_PPC4XX_PIT_STOP_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc4xx_pit_stop",
.sstate = TRACE_PPC4XX_PIT_STOP_ENABLED,
.dstate = &_TRACE_PPC4XX_PIT_STOP_DSTATE
};
TraceEvent _TRACE_PPC4XX_PIT_START_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc4xx_pit_start",
.sstate = TRACE_PPC4XX_PIT_START_ENABLED,
.dstate = &_TRACE_PPC4XX_PIT_START_DSTATE
};
TraceEvent _TRACE_PPC4XX_PIT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc4xx_pit",
.sstate = TRACE_PPC4XX_PIT_ENABLED,
.dstate = &_TRACE_PPC4XX_PIT_DSTATE
};
TraceEvent _TRACE_PPC4XX_WDT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc4xx_wdt",
.sstate = TRACE_PPC4XX_WDT_ENABLED,
.dstate = &_TRACE_PPC4XX_WDT_DSTATE
};
TraceEvent _TRACE_PPC40X_STORE_PIT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc40x_store_pit",
.sstate = TRACE_PPC40X_STORE_PIT_ENABLED,
.dstate = &_TRACE_PPC40X_STORE_PIT_DSTATE
};
TraceEvent _TRACE_PPC40X_STORE_TCR_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc40x_store_tcr",
.sstate = TRACE_PPC40X_STORE_TCR_ENABLED,
.dstate = &_TRACE_PPC40X_STORE_TCR_DSTATE
};
TraceEvent _TRACE_PPC40X_STORE_TSR_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc40x_store_tsr",
.sstate = TRACE_PPC40X_STORE_TSR_ENABLED,
.dstate = &_TRACE_PPC40X_STORE_TSR_DSTATE
};
TraceEvent _TRACE_PPC40X_SET_TB_CLK_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc40x_set_tb_clk",
.sstate = TRACE_PPC40X_SET_TB_CLK_ENABLED,
.dstate = &_TRACE_PPC40X_SET_TB_CLK_DSTATE
};
TraceEvent _TRACE_PPC40X_TIMERS_INIT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc40x_timers_init",
.sstate = TRACE_PPC40X_TIMERS_INIT_ENABLED,
.dstate = &_TRACE_PPC40X_TIMERS_INIT_DSTATE
};
TraceEvent _TRACE_PPC_IRQ_SET_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc_irq_set",
.sstate = TRACE_PPC_IRQ_SET_ENABLED,
.dstate = &_TRACE_PPC_IRQ_SET_DSTATE
};
TraceEvent _TRACE_PPC_IRQ_SET_EXIT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc_irq_set_exit",
.sstate = TRACE_PPC_IRQ_SET_EXIT_ENABLED,
.dstate = &_TRACE_PPC_IRQ_SET_EXIT_DSTATE
};
TraceEvent _TRACE_PPC_IRQ_SET_STATE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc_irq_set_state",
.sstate = TRACE_PPC_IRQ_SET_STATE_ENABLED,
.dstate = &_TRACE_PPC_IRQ_SET_STATE_DSTATE
};
TraceEvent _TRACE_PPC_IRQ_RESET_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc_irq_reset",
.sstate = TRACE_PPC_IRQ_RESET_ENABLED,
.dstate = &_TRACE_PPC_IRQ_RESET_DSTATE
};
TraceEvent _TRACE_PPC_IRQ_CPU_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc_irq_cpu",
.sstate = TRACE_PPC_IRQ_CPU_ENABLED,
.dstate = &_TRACE_PPC_IRQ_CPU_DSTATE
};
TraceEvent _TRACE_PPC_DCR_READ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc_dcr_read",
.sstate = TRACE_PPC_DCR_READ_ENABLED,
.dstate = &_TRACE_PPC_DCR_READ_DSTATE
};
TraceEvent _TRACE_PPC_DCR_WRITE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc_dcr_write",
.sstate = TRACE_PPC_DCR_WRITE_ENABLED,
.dstate = &_TRACE_PPC_DCR_WRITE_DSTATE
};
TraceEvent _TRACE_PREP_SYSTEMIO_READ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "prep_systemio_read",
.sstate = TRACE_PREP_SYSTEMIO_READ_ENABLED,
.dstate = &_TRACE_PREP_SYSTEMIO_READ_DSTATE
};
TraceEvent _TRACE_PREP_SYSTEMIO_WRITE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "prep_systemio_write",
.sstate = TRACE_PREP_SYSTEMIO_WRITE_ENABLED,
.dstate = &_TRACE_PREP_SYSTEMIO_WRITE_DSTATE
};
TraceEvent _TRACE_RS6000MC_ID_READ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "rs6000mc_id_read",
.sstate = TRACE_RS6000MC_ID_READ_ENABLED,
.dstate = &_TRACE_RS6000MC_ID_READ_DSTATE
};
TraceEvent _TRACE_RS6000MC_PRESENCE_READ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "rs6000mc_presence_read",
.sstate = TRACE_RS6000MC_PRESENCE_READ_ENABLED,
.dstate = &_TRACE_RS6000MC_PRESENCE_READ_DSTATE
};
TraceEvent _TRACE_RS6000MC_SIZE_READ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "rs6000mc_size_read",
.sstate = TRACE_RS6000MC_SIZE_READ_ENABLED,
.dstate = &_TRACE_RS6000MC_SIZE_READ_DSTATE
};
TraceEvent _TRACE_RS6000MC_SIZE_WRITE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "rs6000mc_size_write",
.sstate = TRACE_RS6000MC_SIZE_WRITE_ENABLED,
.dstate = &_TRACE_RS6000MC_SIZE_WRITE_DSTATE
};
TraceEvent _TRACE_RS6000MC_PARITY_READ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "rs6000mc_parity_read",
.sstate = TRACE_RS6000MC_PARITY_READ_ENABLED,
.dstate = &_TRACE_RS6000MC_PARITY_READ_DSTATE
};
TraceEvent _TRACE_PPC4XX_PCI_MAP_IRQ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc4xx_pci_map_irq",
.sstate = TRACE_PPC4XX_PCI_MAP_IRQ_ENABLED,
.dstate = &_TRACE_PPC4XX_PCI_MAP_IRQ_DSTATE
};
TraceEvent _TRACE_PPC4XX_PCI_SET_IRQ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc4xx_pci_set_irq",
.sstate = TRACE_PPC4XX_PCI_SET_IRQ_ENABLED,
.dstate = &_TRACE_PPC4XX_PCI_SET_IRQ_DSTATE
};
TraceEvent _TRACE_PPC440_PCIX_MAP_IRQ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc440_pcix_map_irq",
.sstate = TRACE_PPC440_PCIX_MAP_IRQ_ENABLED,
.dstate = &_TRACE_PPC440_PCIX_MAP_IRQ_DSTATE
};
TraceEvent _TRACE_PPC440_PCIX_SET_IRQ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc440_pcix_set_irq",
.sstate = TRACE_PPC440_PCIX_SET_IRQ_ENABLED,
.dstate = &_TRACE_PPC440_PCIX_SET_IRQ_DSTATE
};
TraceEvent _TRACE_PPC440_PCIX_UPDATE_PIM_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc440_pcix_update_pim",
.sstate = TRACE_PPC440_PCIX_UPDATE_PIM_ENABLED,
.dstate = &_TRACE_PPC440_PCIX_UPDATE_PIM_DSTATE
};
TraceEvent _TRACE_PPC440_PCIX_UPDATE_POM_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc440_pcix_update_pom",
.sstate = TRACE_PPC440_PCIX_UPDATE_POM_ENABLED,
.dstate = &_TRACE_PPC440_PCIX_UPDATE_POM_DSTATE
};
TraceEvent _TRACE_PPC440_PCIX_REG_READ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc440_pcix_reg_read",
.sstate = TRACE_PPC440_PCIX_REG_READ_ENABLED,
.dstate = &_TRACE_PPC440_PCIX_REG_READ_DSTATE
};
TraceEvent _TRACE_PPC440_PCIX_REG_WRITE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc440_pcix_reg_write",
.sstate = TRACE_PPC440_PCIX_REG_WRITE_ENABLED,
.dstate = &_TRACE_PPC440_PCIX_REG_WRITE_DSTATE
};
TraceEvent _TRACE_OPBA_READB_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "opba_readb",
.sstate = TRACE_OPBA_READB_ENABLED,
.dstate = &_TRACE_OPBA_READB_DSTATE
};
TraceEvent _TRACE_OPBA_WRITEB_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "opba_writeb",
.sstate = TRACE_OPBA_WRITEB_ENABLED,
.dstate = &_TRACE_OPBA_WRITEB_DSTATE
};
TraceEvent _TRACE_OPBA_INIT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "opba_init",
.sstate = TRACE_OPBA_INIT_ENABLED,
.dstate = &_TRACE_OPBA_INIT_DSTATE
};
TraceEvent _TRACE_PPC405_GPIO_READ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc405_gpio_read",
.sstate = TRACE_PPC405_GPIO_READ_ENABLED,
.dstate = &_TRACE_PPC405_GPIO_READ_DSTATE
};
TraceEvent _TRACE_PPC405_GPIO_WRITE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc405_gpio_write",
.sstate = TRACE_PPC405_GPIO_WRITE_ENABLED,
.dstate = &_TRACE_PPC405_GPIO_WRITE_DSTATE
};
TraceEvent _TRACE_PPC405_GPIO_INIT_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc405_gpio_init",
.sstate = TRACE_PPC405_GPIO_INIT_ENABLED,
.dstate = &_TRACE_PPC405_GPIO_INIT_DSTATE
};
TraceEvent _TRACE_OCM_UPDATE_MAPPINGS_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ocm_update_mappings",
.sstate = TRACE_OCM_UPDATE_MAPPINGS_ENABLED,
.dstate = &_TRACE_OCM_UPDATE_MAPPINGS_DSTATE
};
TraceEvent _TRACE_OCM_MAP_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ocm_map",
.sstate = TRACE_OCM_MAP_ENABLED,
.dstate = &_TRACE_OCM_MAP_DSTATE
};
TraceEvent _TRACE_OCM_UNMAP_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ocm_unmap",
.sstate = TRACE_OCM_UNMAP_ENABLED,
.dstate = &_TRACE_OCM_UNMAP_DSTATE
};
TraceEvent _TRACE_PPC4XX_GPT_READ_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,
.name = "ppc4xx_gpt_read",
.sstate = TRACE_PPC4XX_GPT_READ_ENABLED,
.dstate = &_TRACE_PPC4XX_GPT_READ_DSTATE
};
TraceEvent _TRACE_PPC4XX_GPT_WRITE_EVENT = {
.id = 0,
.vcpu_id = TRACE_VCPU_EVENT_NONE,