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trace-hw_arm.h
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trace-hw_arm.h
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/* This file is autogenerated by tracetool, do not edit. */
#ifndef TRACE_HW_ARM_GENERATED_TRACERS_H
#define TRACE_HW_ARM_GENERATED_TRACERS_H
#include "trace/control.h"
extern TraceEvent _TRACE_VIRT_ACPI_SETUP_EVENT;
extern TraceEvent _TRACE_SMMU_ADD_MR_EVENT;
extern TraceEvent _TRACE_SMMU_PTW_LEVEL_EVENT;
extern TraceEvent _TRACE_SMMU_PTW_INVALID_PTE_EVENT;
extern TraceEvent _TRACE_SMMU_PTW_PAGE_PTE_EVENT;
extern TraceEvent _TRACE_SMMU_PTW_BLOCK_PTE_EVENT;
extern TraceEvent _TRACE_SMMU_GET_PTE_EVENT;
extern TraceEvent _TRACE_SMMU_IOTLB_INV_ALL_EVENT;
extern TraceEvent _TRACE_SMMU_IOTLB_INV_ASID_EVENT;
extern TraceEvent _TRACE_SMMU_IOTLB_INV_IOVA_EVENT;
extern TraceEvent _TRACE_SMMU_INV_NOTIFIERS_MR_EVENT;
extern TraceEvent _TRACE_SMMU_IOTLB_LOOKUP_HIT_EVENT;
extern TraceEvent _TRACE_SMMU_IOTLB_LOOKUP_MISS_EVENT;
extern TraceEvent _TRACE_SMMU_IOTLB_INSERT_EVENT;
extern TraceEvent _TRACE_SMMUV3_READ_MMIO_EVENT;
extern TraceEvent _TRACE_SMMUV3_TRIGGER_IRQ_EVENT;
extern TraceEvent _TRACE_SMMUV3_WRITE_GERROR_EVENT;
extern TraceEvent _TRACE_SMMUV3_WRITE_GERRORN_EVENT;
extern TraceEvent _TRACE_SMMUV3_UNHANDLED_CMD_EVENT;
extern TraceEvent _TRACE_SMMUV3_CMDQ_CONSUME_EVENT;
extern TraceEvent _TRACE_SMMUV3_CMDQ_OPCODE_EVENT;
extern TraceEvent _TRACE_SMMUV3_CMDQ_CONSUME_OUT_EVENT;
extern TraceEvent _TRACE_SMMUV3_CMDQ_CONSUME_ERROR_EVENT;
extern TraceEvent _TRACE_SMMUV3_WRITE_MMIO_EVENT;
extern TraceEvent _TRACE_SMMUV3_RECORD_EVENT_EVENT;
extern TraceEvent _TRACE_SMMUV3_FIND_STE_EVENT;
extern TraceEvent _TRACE_SMMUV3_FIND_STE_2LVL_EVENT;
extern TraceEvent _TRACE_SMMUV3_GET_STE_EVENT;
extern TraceEvent _TRACE_SMMUV3_TRANSLATE_DISABLE_EVENT;
extern TraceEvent _TRACE_SMMUV3_TRANSLATE_BYPASS_EVENT;
extern TraceEvent _TRACE_SMMUV3_TRANSLATE_ABORT_EVENT;
extern TraceEvent _TRACE_SMMUV3_TRANSLATE_SUCCESS_EVENT;
extern TraceEvent _TRACE_SMMUV3_GET_CD_EVENT;
extern TraceEvent _TRACE_SMMUV3_DECODE_CD_EVENT;
extern TraceEvent _TRACE_SMMUV3_DECODE_CD_TT_EVENT;
extern TraceEvent _TRACE_SMMUV3_CMDQ_CFGI_STE_EVENT;
extern TraceEvent _TRACE_SMMUV3_CMDQ_CFGI_STE_RANGE_EVENT;
extern TraceEvent _TRACE_SMMUV3_CMDQ_CFGI_CD_EVENT;
extern TraceEvent _TRACE_SMMUV3_CONFIG_CACHE_HIT_EVENT;
extern TraceEvent _TRACE_SMMUV3_CONFIG_CACHE_MISS_EVENT;
extern TraceEvent _TRACE_SMMUV3_S1_RANGE_INVAL_EVENT;
extern TraceEvent _TRACE_SMMUV3_CMDQ_TLBI_NH_EVENT;
extern TraceEvent _TRACE_SMMUV3_CMDQ_TLBI_NH_ASID_EVENT;
extern TraceEvent _TRACE_SMMUV3_CONFIG_CACHE_INV_EVENT;
extern TraceEvent _TRACE_SMMUV3_NOTIFY_FLAG_ADD_EVENT;
extern TraceEvent _TRACE_SMMUV3_NOTIFY_FLAG_DEL_EVENT;
extern TraceEvent _TRACE_SMMUV3_INV_NOTIFIERS_IOVA_EVENT;
extern uint16_t _TRACE_VIRT_ACPI_SETUP_DSTATE;
extern uint16_t _TRACE_SMMU_ADD_MR_DSTATE;
extern uint16_t _TRACE_SMMU_PTW_LEVEL_DSTATE;
extern uint16_t _TRACE_SMMU_PTW_INVALID_PTE_DSTATE;
extern uint16_t _TRACE_SMMU_PTW_PAGE_PTE_DSTATE;
extern uint16_t _TRACE_SMMU_PTW_BLOCK_PTE_DSTATE;
extern uint16_t _TRACE_SMMU_GET_PTE_DSTATE;
extern uint16_t _TRACE_SMMU_IOTLB_INV_ALL_DSTATE;
extern uint16_t _TRACE_SMMU_IOTLB_INV_ASID_DSTATE;
extern uint16_t _TRACE_SMMU_IOTLB_INV_IOVA_DSTATE;
extern uint16_t _TRACE_SMMU_INV_NOTIFIERS_MR_DSTATE;
extern uint16_t _TRACE_SMMU_IOTLB_LOOKUP_HIT_DSTATE;
extern uint16_t _TRACE_SMMU_IOTLB_LOOKUP_MISS_DSTATE;
extern uint16_t _TRACE_SMMU_IOTLB_INSERT_DSTATE;
extern uint16_t _TRACE_SMMUV3_READ_MMIO_DSTATE;
extern uint16_t _TRACE_SMMUV3_TRIGGER_IRQ_DSTATE;
extern uint16_t _TRACE_SMMUV3_WRITE_GERROR_DSTATE;
extern uint16_t _TRACE_SMMUV3_WRITE_GERRORN_DSTATE;
extern uint16_t _TRACE_SMMUV3_UNHANDLED_CMD_DSTATE;
extern uint16_t _TRACE_SMMUV3_CMDQ_CONSUME_DSTATE;
extern uint16_t _TRACE_SMMUV3_CMDQ_OPCODE_DSTATE;
extern uint16_t _TRACE_SMMUV3_CMDQ_CONSUME_OUT_DSTATE;
extern uint16_t _TRACE_SMMUV3_CMDQ_CONSUME_ERROR_DSTATE;
extern uint16_t _TRACE_SMMUV3_WRITE_MMIO_DSTATE;
extern uint16_t _TRACE_SMMUV3_RECORD_EVENT_DSTATE;
extern uint16_t _TRACE_SMMUV3_FIND_STE_DSTATE;
extern uint16_t _TRACE_SMMUV3_FIND_STE_2LVL_DSTATE;
extern uint16_t _TRACE_SMMUV3_GET_STE_DSTATE;
extern uint16_t _TRACE_SMMUV3_TRANSLATE_DISABLE_DSTATE;
extern uint16_t _TRACE_SMMUV3_TRANSLATE_BYPASS_DSTATE;
extern uint16_t _TRACE_SMMUV3_TRANSLATE_ABORT_DSTATE;
extern uint16_t _TRACE_SMMUV3_TRANSLATE_SUCCESS_DSTATE;
extern uint16_t _TRACE_SMMUV3_GET_CD_DSTATE;
extern uint16_t _TRACE_SMMUV3_DECODE_CD_DSTATE;
extern uint16_t _TRACE_SMMUV3_DECODE_CD_TT_DSTATE;
extern uint16_t _TRACE_SMMUV3_CMDQ_CFGI_STE_DSTATE;
extern uint16_t _TRACE_SMMUV3_CMDQ_CFGI_STE_RANGE_DSTATE;
extern uint16_t _TRACE_SMMUV3_CMDQ_CFGI_CD_DSTATE;
extern uint16_t _TRACE_SMMUV3_CONFIG_CACHE_HIT_DSTATE;
extern uint16_t _TRACE_SMMUV3_CONFIG_CACHE_MISS_DSTATE;
extern uint16_t _TRACE_SMMUV3_S1_RANGE_INVAL_DSTATE;
extern uint16_t _TRACE_SMMUV3_CMDQ_TLBI_NH_DSTATE;
extern uint16_t _TRACE_SMMUV3_CMDQ_TLBI_NH_ASID_DSTATE;
extern uint16_t _TRACE_SMMUV3_CONFIG_CACHE_INV_DSTATE;
extern uint16_t _TRACE_SMMUV3_NOTIFY_FLAG_ADD_DSTATE;
extern uint16_t _TRACE_SMMUV3_NOTIFY_FLAG_DEL_DSTATE;
extern uint16_t _TRACE_SMMUV3_INV_NOTIFIERS_IOVA_DSTATE;
#define TRACE_VIRT_ACPI_SETUP_ENABLED 1
#define TRACE_SMMU_ADD_MR_ENABLED 1
#define TRACE_SMMU_PTW_LEVEL_ENABLED 1
#define TRACE_SMMU_PTW_INVALID_PTE_ENABLED 1
#define TRACE_SMMU_PTW_PAGE_PTE_ENABLED 1
#define TRACE_SMMU_PTW_BLOCK_PTE_ENABLED 1
#define TRACE_SMMU_GET_PTE_ENABLED 1
#define TRACE_SMMU_IOTLB_INV_ALL_ENABLED 1
#define TRACE_SMMU_IOTLB_INV_ASID_ENABLED 1
#define TRACE_SMMU_IOTLB_INV_IOVA_ENABLED 1
#define TRACE_SMMU_INV_NOTIFIERS_MR_ENABLED 1
#define TRACE_SMMU_IOTLB_LOOKUP_HIT_ENABLED 1
#define TRACE_SMMU_IOTLB_LOOKUP_MISS_ENABLED 1
#define TRACE_SMMU_IOTLB_INSERT_ENABLED 1
#define TRACE_SMMUV3_READ_MMIO_ENABLED 1
#define TRACE_SMMUV3_TRIGGER_IRQ_ENABLED 1
#define TRACE_SMMUV3_WRITE_GERROR_ENABLED 1
#define TRACE_SMMUV3_WRITE_GERRORN_ENABLED 1
#define TRACE_SMMUV3_UNHANDLED_CMD_ENABLED 1
#define TRACE_SMMUV3_CMDQ_CONSUME_ENABLED 1
#define TRACE_SMMUV3_CMDQ_OPCODE_ENABLED 1
#define TRACE_SMMUV3_CMDQ_CONSUME_OUT_ENABLED 1
#define TRACE_SMMUV3_CMDQ_CONSUME_ERROR_ENABLED 1
#define TRACE_SMMUV3_WRITE_MMIO_ENABLED 1
#define TRACE_SMMUV3_RECORD_EVENT_ENABLED 1
#define TRACE_SMMUV3_FIND_STE_ENABLED 1
#define TRACE_SMMUV3_FIND_STE_2LVL_ENABLED 1
#define TRACE_SMMUV3_GET_STE_ENABLED 1
#define TRACE_SMMUV3_TRANSLATE_DISABLE_ENABLED 1
#define TRACE_SMMUV3_TRANSLATE_BYPASS_ENABLED 1
#define TRACE_SMMUV3_TRANSLATE_ABORT_ENABLED 1
#define TRACE_SMMUV3_TRANSLATE_SUCCESS_ENABLED 1
#define TRACE_SMMUV3_GET_CD_ENABLED 1
#define TRACE_SMMUV3_DECODE_CD_ENABLED 1
#define TRACE_SMMUV3_DECODE_CD_TT_ENABLED 1
#define TRACE_SMMUV3_CMDQ_CFGI_STE_ENABLED 1
#define TRACE_SMMUV3_CMDQ_CFGI_STE_RANGE_ENABLED 1
#define TRACE_SMMUV3_CMDQ_CFGI_CD_ENABLED 1
#define TRACE_SMMUV3_CONFIG_CACHE_HIT_ENABLED 1
#define TRACE_SMMUV3_CONFIG_CACHE_MISS_ENABLED 1
#define TRACE_SMMUV3_S1_RANGE_INVAL_ENABLED 1
#define TRACE_SMMUV3_CMDQ_TLBI_NH_ENABLED 1
#define TRACE_SMMUV3_CMDQ_TLBI_NH_ASID_ENABLED 1
#define TRACE_SMMUV3_CONFIG_CACHE_INV_ENABLED 1
#define TRACE_SMMUV3_NOTIFY_FLAG_ADD_ENABLED 1
#define TRACE_SMMUV3_NOTIFY_FLAG_DEL_ENABLED 1
#define TRACE_SMMUV3_INV_NOTIFIERS_IOVA_ENABLED 1
#include "qemu/log-for-trace.h"
#include "qemu/error-report.h"
#define TRACE_VIRT_ACPI_SETUP_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_VIRT_ACPI_SETUP) || \
false)
static inline void _nocheck__trace_virt_acpi_setup(void)
{
if (trace_event_get_state(TRACE_VIRT_ACPI_SETUP) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 4 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:virt_acpi_setup " "No fw cfg or ACPI disabled. Bailing out." "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
);
#line 169 "trace/trace-hw_arm.h"
} else {
#line 4 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("virt_acpi_setup " "No fw cfg or ACPI disabled. Bailing out." "\n");
#line 173 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_virt_acpi_setup(void)
{
if (true) {
_nocheck__trace_virt_acpi_setup();
}
}
#define TRACE_SMMU_ADD_MR_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMU_ADD_MR) || \
false)
static inline void _nocheck__trace_smmu_add_mr(const char * name)
{
if (trace_event_get_state(TRACE_SMMU_ADD_MR) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 7 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmu_add_mr " "%s" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, name);
#line 200 "trace/trace-hw_arm.h"
} else {
#line 7 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmu_add_mr " "%s" "\n", name);
#line 204 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmu_add_mr(const char * name)
{
if (true) {
_nocheck__trace_smmu_add_mr(name);
}
}
#define TRACE_SMMU_PTW_LEVEL_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMU_PTW_LEVEL) || \
false)
static inline void _nocheck__trace_smmu_ptw_level(int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte)
{
if (trace_event_get_state(TRACE_SMMU_PTW_LEVEL) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 8 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmu_ptw_level " "level=%d iova=0x%"PRIx64" subpage_sz=0x%zx baseaddr=0x%"PRIx64" offset=%d => pte=0x%"PRIx64 "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, level, iova, subpage_size, baseaddr, offset, pte);
#line 231 "trace/trace-hw_arm.h"
} else {
#line 8 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmu_ptw_level " "level=%d iova=0x%"PRIx64" subpage_sz=0x%zx baseaddr=0x%"PRIx64" offset=%d => pte=0x%"PRIx64 "\n", level, iova, subpage_size, baseaddr, offset, pte);
#line 235 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmu_ptw_level(int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte)
{
if (true) {
_nocheck__trace_smmu_ptw_level(level, iova, subpage_size, baseaddr, offset, pte);
}
}
#define TRACE_SMMU_PTW_INVALID_PTE_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMU_PTW_INVALID_PTE) || \
false)
static inline void _nocheck__trace_smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint32_t offset, uint64_t pte)
{
if (trace_event_get_state(TRACE_SMMU_PTW_INVALID_PTE) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 9 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmu_ptw_invalid_pte " "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" offset=%d pte=0x%"PRIx64 "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, stage, level, baseaddr, pteaddr, offset, pte);
#line 262 "trace/trace-hw_arm.h"
} else {
#line 9 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmu_ptw_invalid_pte " "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" offset=%d pte=0x%"PRIx64 "\n", stage, level, baseaddr, pteaddr, offset, pte);
#line 266 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint32_t offset, uint64_t pte)
{
if (true) {
_nocheck__trace_smmu_ptw_invalid_pte(stage, level, baseaddr, pteaddr, offset, pte);
}
}
#define TRACE_SMMU_PTW_PAGE_PTE_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMU_PTW_PAGE_PTE) || \
false)
static inline void _nocheck__trace_smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address)
{
if (trace_event_get_state(TRACE_SMMU_PTW_PAGE_PTE) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 10 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmu_ptw_page_pte " "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64 "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, stage, level, iova, baseaddr, pteaddr, pte, address);
#line 293 "trace/trace-hw_arm.h"
} else {
#line 10 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmu_ptw_page_pte " "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64 "\n", stage, level, iova, baseaddr, pteaddr, pte, address);
#line 297 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address)
{
if (true) {
_nocheck__trace_smmu_ptw_page_pte(stage, level, iova, baseaddr, pteaddr, pte, address);
}
}
#define TRACE_SMMU_PTW_BLOCK_PTE_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMU_PTW_BLOCK_PTE) || \
false)
static inline void _nocheck__trace_smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb)
{
if (trace_event_get_state(TRACE_SMMU_PTW_BLOCK_PTE) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 11 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmu_ptw_block_pte " "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, stage, level, baseaddr, pteaddr, pte, iova, gpa, bsize_mb);
#line 324 "trace/trace-hw_arm.h"
} else {
#line 11 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmu_ptw_block_pte " "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB" "\n", stage, level, baseaddr, pteaddr, pte, iova, gpa, bsize_mb);
#line 328 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb)
{
if (true) {
_nocheck__trace_smmu_ptw_block_pte(stage, level, baseaddr, pteaddr, pte, iova, gpa, bsize_mb);
}
}
#define TRACE_SMMU_GET_PTE_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMU_GET_PTE) || \
false)
static inline void _nocheck__trace_smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte)
{
if (trace_event_get_state(TRACE_SMMU_GET_PTE) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 12 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmu_get_pte " "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64 "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, baseaddr, index, pteaddr, pte);
#line 355 "trace/trace-hw_arm.h"
} else {
#line 12 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmu_get_pte " "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64 "\n", baseaddr, index, pteaddr, pte);
#line 359 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte)
{
if (true) {
_nocheck__trace_smmu_get_pte(baseaddr, index, pteaddr, pte);
}
}
#define TRACE_SMMU_IOTLB_INV_ALL_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMU_IOTLB_INV_ALL) || \
false)
static inline void _nocheck__trace_smmu_iotlb_inv_all(void)
{
if (trace_event_get_state(TRACE_SMMU_IOTLB_INV_ALL) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 13 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmu_iotlb_inv_all " "IOTLB invalidate all" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
);
#line 386 "trace/trace-hw_arm.h"
} else {
#line 13 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmu_iotlb_inv_all " "IOTLB invalidate all" "\n");
#line 390 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmu_iotlb_inv_all(void)
{
if (true) {
_nocheck__trace_smmu_iotlb_inv_all();
}
}
#define TRACE_SMMU_IOTLB_INV_ASID_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMU_IOTLB_INV_ASID) || \
false)
static inline void _nocheck__trace_smmu_iotlb_inv_asid(uint16_t asid)
{
if (trace_event_get_state(TRACE_SMMU_IOTLB_INV_ASID) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 14 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmu_iotlb_inv_asid " "IOTLB invalidate asid=%d" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, asid);
#line 417 "trace/trace-hw_arm.h"
} else {
#line 14 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmu_iotlb_inv_asid " "IOTLB invalidate asid=%d" "\n", asid);
#line 421 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmu_iotlb_inv_asid(uint16_t asid)
{
if (true) {
_nocheck__trace_smmu_iotlb_inv_asid(asid);
}
}
#define TRACE_SMMU_IOTLB_INV_IOVA_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMU_IOTLB_INV_IOVA) || \
false)
static inline void _nocheck__trace_smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr)
{
if (trace_event_get_state(TRACE_SMMU_IOTLB_INV_IOVA) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 15 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmu_iotlb_inv_iova " "IOTLB invalidate asid=%d addr=0x%"PRIx64 "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, asid, addr);
#line 448 "trace/trace-hw_arm.h"
} else {
#line 15 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmu_iotlb_inv_iova " "IOTLB invalidate asid=%d addr=0x%"PRIx64 "\n", asid, addr);
#line 452 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr)
{
if (true) {
_nocheck__trace_smmu_iotlb_inv_iova(asid, addr);
}
}
#define TRACE_SMMU_INV_NOTIFIERS_MR_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMU_INV_NOTIFIERS_MR) || \
false)
static inline void _nocheck__trace_smmu_inv_notifiers_mr(const char * name)
{
if (trace_event_get_state(TRACE_SMMU_INV_NOTIFIERS_MR) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 16 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmu_inv_notifiers_mr " "iommu mr=%s" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, name);
#line 479 "trace/trace-hw_arm.h"
} else {
#line 16 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmu_inv_notifiers_mr " "iommu mr=%s" "\n", name);
#line 483 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmu_inv_notifiers_mr(const char * name)
{
if (true) {
_nocheck__trace_smmu_inv_notifiers_mr(name);
}
}
#define TRACE_SMMU_IOTLB_LOOKUP_HIT_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMU_IOTLB_LOOKUP_HIT) || \
false)
static inline void _nocheck__trace_smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p)
{
if (trace_event_get_state(TRACE_SMMU_IOTLB_LOOKUP_HIT) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 17 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmu_iotlb_lookup_hit " "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, asid, addr, hit, miss, p);
#line 510 "trace/trace-hw_arm.h"
} else {
#line 17 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmu_iotlb_lookup_hit " "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" "\n", asid, addr, hit, miss, p);
#line 514 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p)
{
if (true) {
_nocheck__trace_smmu_iotlb_lookup_hit(asid, addr, hit, miss, p);
}
}
#define TRACE_SMMU_IOTLB_LOOKUP_MISS_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMU_IOTLB_LOOKUP_MISS) || \
false)
static inline void _nocheck__trace_smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p)
{
if (trace_event_get_state(TRACE_SMMU_IOTLB_LOOKUP_MISS) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 18 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmu_iotlb_lookup_miss " "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, asid, addr, hit, miss, p);
#line 541 "trace/trace-hw_arm.h"
} else {
#line 18 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmu_iotlb_lookup_miss " "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" "\n", asid, addr, hit, miss, p);
#line 545 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p)
{
if (true) {
_nocheck__trace_smmu_iotlb_lookup_miss(asid, addr, hit, miss, p);
}
}
#define TRACE_SMMU_IOTLB_INSERT_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMU_IOTLB_INSERT) || \
false)
static inline void _nocheck__trace_smmu_iotlb_insert(uint16_t asid, uint64_t addr, uint8_t tg, uint8_t level)
{
if (trace_event_get_state(TRACE_SMMU_IOTLB_INSERT) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 19 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmu_iotlb_insert " "IOTLB ++ asid=%d addr=0x%"PRIx64" tg=%d level=%d" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, asid, addr, tg, level);
#line 572 "trace/trace-hw_arm.h"
} else {
#line 19 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmu_iotlb_insert " "IOTLB ++ asid=%d addr=0x%"PRIx64" tg=%d level=%d" "\n", asid, addr, tg, level);
#line 576 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmu_iotlb_insert(uint16_t asid, uint64_t addr, uint8_t tg, uint8_t level)
{
if (true) {
_nocheck__trace_smmu_iotlb_insert(asid, addr, tg, level);
}
}
#define TRACE_SMMUV3_READ_MMIO_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMUV3_READ_MMIO) || \
false)
static inline void _nocheck__trace_smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r)
{
if (trace_event_get_state(TRACE_SMMUV3_READ_MMIO) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 22 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmuv3_read_mmio " "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, addr, val, size, r);
#line 603 "trace/trace-hw_arm.h"
} else {
#line 22 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmuv3_read_mmio " "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" "\n", addr, val, size, r);
#line 607 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r)
{
if (true) {
_nocheck__trace_smmuv3_read_mmio(addr, val, size, r);
}
}
#define TRACE_SMMUV3_TRIGGER_IRQ_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMUV3_TRIGGER_IRQ) || \
false)
static inline void _nocheck__trace_smmuv3_trigger_irq(int irq)
{
if (trace_event_get_state(TRACE_SMMUV3_TRIGGER_IRQ) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 23 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmuv3_trigger_irq " "irq=%d" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, irq);
#line 634 "trace/trace-hw_arm.h"
} else {
#line 23 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmuv3_trigger_irq " "irq=%d" "\n", irq);
#line 638 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmuv3_trigger_irq(int irq)
{
if (true) {
_nocheck__trace_smmuv3_trigger_irq(irq);
}
}
#define TRACE_SMMUV3_WRITE_GERROR_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMUV3_WRITE_GERROR) || \
false)
static inline void _nocheck__trace_smmuv3_write_gerror(uint32_t toggled, uint32_t gerror)
{
if (trace_event_get_state(TRACE_SMMUV3_WRITE_GERROR) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 24 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmuv3_write_gerror " "toggled=0x%x, new GERROR=0x%x" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, toggled, gerror);
#line 665 "trace/trace-hw_arm.h"
} else {
#line 24 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmuv3_write_gerror " "toggled=0x%x, new GERROR=0x%x" "\n", toggled, gerror);
#line 669 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmuv3_write_gerror(uint32_t toggled, uint32_t gerror)
{
if (true) {
_nocheck__trace_smmuv3_write_gerror(toggled, gerror);
}
}
#define TRACE_SMMUV3_WRITE_GERRORN_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMUV3_WRITE_GERRORN) || \
false)
static inline void _nocheck__trace_smmuv3_write_gerrorn(uint32_t acked, uint32_t gerrorn)
{
if (trace_event_get_state(TRACE_SMMUV3_WRITE_GERRORN) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 25 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmuv3_write_gerrorn " "acked=0x%x, new GERRORN=0x%x" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, acked, gerrorn);
#line 696 "trace/trace-hw_arm.h"
} else {
#line 25 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmuv3_write_gerrorn " "acked=0x%x, new GERRORN=0x%x" "\n", acked, gerrorn);
#line 700 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmuv3_write_gerrorn(uint32_t acked, uint32_t gerrorn)
{
if (true) {
_nocheck__trace_smmuv3_write_gerrorn(acked, gerrorn);
}
}
#define TRACE_SMMUV3_UNHANDLED_CMD_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMUV3_UNHANDLED_CMD) || \
false)
static inline void _nocheck__trace_smmuv3_unhandled_cmd(uint32_t type)
{
if (trace_event_get_state(TRACE_SMMUV3_UNHANDLED_CMD) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 26 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmuv3_unhandled_cmd " "Unhandled command type=%d" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, type);
#line 727 "trace/trace-hw_arm.h"
} else {
#line 26 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmuv3_unhandled_cmd " "Unhandled command type=%d" "\n", type);
#line 731 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmuv3_unhandled_cmd(uint32_t type)
{
if (true) {
_nocheck__trace_smmuv3_unhandled_cmd(type);
}
}
#define TRACE_SMMUV3_CMDQ_CONSUME_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMUV3_CMDQ_CONSUME) || \
false)
static inline void _nocheck__trace_smmuv3_cmdq_consume(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap)
{
if (trace_event_get_state(TRACE_SMMUV3_CMDQ_CONSUME) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 27 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmuv3_cmdq_consume " "prod=%d cons=%d prod.wrap=%d cons.wrap=%d" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, prod, cons, prod_wrap, cons_wrap);
#line 758 "trace/trace-hw_arm.h"
} else {
#line 27 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmuv3_cmdq_consume " "prod=%d cons=%d prod.wrap=%d cons.wrap=%d" "\n", prod, cons, prod_wrap, cons_wrap);
#line 762 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmuv3_cmdq_consume(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap)
{
if (true) {
_nocheck__trace_smmuv3_cmdq_consume(prod, cons, prod_wrap, cons_wrap);
}
}
#define TRACE_SMMUV3_CMDQ_OPCODE_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMUV3_CMDQ_OPCODE) || \
false)
static inline void _nocheck__trace_smmuv3_cmdq_opcode(const char * opcode)
{
if (trace_event_get_state(TRACE_SMMUV3_CMDQ_OPCODE) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 28 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmuv3_cmdq_opcode " "<--- %s" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, opcode);
#line 789 "trace/trace-hw_arm.h"
} else {
#line 28 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmuv3_cmdq_opcode " "<--- %s" "\n", opcode);
#line 793 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmuv3_cmdq_opcode(const char * opcode)
{
if (true) {
_nocheck__trace_smmuv3_cmdq_opcode(opcode);
}
}
#define TRACE_SMMUV3_CMDQ_CONSUME_OUT_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMUV3_CMDQ_CONSUME_OUT) || \
false)
static inline void _nocheck__trace_smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap)
{
if (trace_event_get_state(TRACE_SMMUV3_CMDQ_CONSUME_OUT) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 29 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmuv3_cmdq_consume_out " "prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d " "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, prod, cons, prod_wrap, cons_wrap);
#line 820 "trace/trace-hw_arm.h"
} else {
#line 29 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmuv3_cmdq_consume_out " "prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d " "\n", prod, cons, prod_wrap, cons_wrap);
#line 824 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap)
{
if (true) {
_nocheck__trace_smmuv3_cmdq_consume_out(prod, cons, prod_wrap, cons_wrap);
}
}
#define TRACE_SMMUV3_CMDQ_CONSUME_ERROR_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMUV3_CMDQ_CONSUME_ERROR) || \
false)
static inline void _nocheck__trace_smmuv3_cmdq_consume_error(const char * cmd_name, uint8_t cmd_error)
{
if (trace_event_get_state(TRACE_SMMUV3_CMDQ_CONSUME_ERROR) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 30 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmuv3_cmdq_consume_error " "Error on %s command execution: %d" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, cmd_name, cmd_error);
#line 851 "trace/trace-hw_arm.h"
} else {
#line 30 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmuv3_cmdq_consume_error " "Error on %s command execution: %d" "\n", cmd_name, cmd_error);
#line 855 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmuv3_cmdq_consume_error(const char * cmd_name, uint8_t cmd_error)
{
if (true) {
_nocheck__trace_smmuv3_cmdq_consume_error(cmd_name, cmd_error);
}
}
#define TRACE_SMMUV3_WRITE_MMIO_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMUV3_WRITE_MMIO) || \
false)
static inline void _nocheck__trace_smmuv3_write_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r)
{
if (trace_event_get_state(TRACE_SMMUV3_WRITE_MMIO) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 31 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmuv3_write_mmio " "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, addr, val, size, r);
#line 882 "trace/trace-hw_arm.h"
} else {
#line 31 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmuv3_write_mmio " "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" "\n", addr, val, size, r);
#line 886 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmuv3_write_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r)
{
if (true) {
_nocheck__trace_smmuv3_write_mmio(addr, val, size, r);
}
}
#define TRACE_SMMUV3_RECORD_EVENT_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMUV3_RECORD_EVENT) || \
false)
static inline void _nocheck__trace_smmuv3_record_event(const char * type, uint32_t sid)
{
if (trace_event_get_state(TRACE_SMMUV3_RECORD_EVENT) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 32 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmuv3_record_event " "%s sid=0x%x" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, type, sid);
#line 913 "trace/trace-hw_arm.h"
} else {
#line 32 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmuv3_record_event " "%s sid=0x%x" "\n", type, sid);
#line 917 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmuv3_record_event(const char * type, uint32_t sid)
{
if (true) {
_nocheck__trace_smmuv3_record_event(type, sid);
}
}
#define TRACE_SMMUV3_FIND_STE_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMUV3_FIND_STE) || \
false)
static inline void _nocheck__trace_smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split)
{
if (trace_event_get_state(TRACE_SMMUV3_FIND_STE) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 33 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmuv3_find_ste " "sid=0x%x features:0x%x, sid_split:0x%x" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, sid, features, sid_split);
#line 944 "trace/trace-hw_arm.h"
} else {
#line 33 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmuv3_find_ste " "sid=0x%x features:0x%x, sid_split:0x%x" "\n", sid, features, sid_split);
#line 948 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split)
{
if (true) {
_nocheck__trace_smmuv3_find_ste(sid, features, sid_split);
}
}
#define TRACE_SMMUV3_FIND_STE_2LVL_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMUV3_FIND_STE_2LVL) || \
false)
static inline void _nocheck__trace_smmuv3_find_ste_2lvl(uint64_t strtab_base, uint64_t l1ptr, int l1_ste_offset, uint64_t l2ptr, int l2_ste_offset, int max_l2_ste)
{
if (trace_event_get_state(TRACE_SMMUV3_FIND_STE_2LVL) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 34 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("%d@%zu.%06zu:smmuv3_find_ste_2lvl " "strtab_base:0x%"PRIx64" l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64" l2_off:0x%x max_l2_ste:%d" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, strtab_base, l1ptr, l1_ste_offset, l2ptr, l2_ste_offset, max_l2_ste);
#line 975 "trace/trace-hw_arm.h"
} else {
#line 34 "/home/inhoinno/FEMU/hw/arm/trace-events"
qemu_log("smmuv3_find_ste_2lvl " "strtab_base:0x%"PRIx64" l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64" l2_off:0x%x max_l2_ste:%d" "\n", strtab_base, l1ptr, l1_ste_offset, l2ptr, l2_ste_offset, max_l2_ste);
#line 979 "trace/trace-hw_arm.h"
}
}
}
static inline void trace_smmuv3_find_ste_2lvl(uint64_t strtab_base, uint64_t l1ptr, int l1_ste_offset, uint64_t l2ptr, int l2_ste_offset, int max_l2_ste)
{
if (true) {
_nocheck__trace_smmuv3_find_ste_2lvl(strtab_base, l1ptr, l1_ste_offset, l2ptr, l2_ste_offset, max_l2_ste);
}
}
#define TRACE_SMMUV3_GET_STE_BACKEND_DSTATE() ( \
trace_event_get_state_dynamic_by_id(TRACE_SMMUV3_GET_STE) || \
false)
static inline void _nocheck__trace_smmuv3_get_ste(uint64_t addr)
{
if (trace_event_get_state(TRACE_SMMUV3_GET_STE) && qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
#line 35 "/home/inhoinno/FEMU/hw/arm/trace-events"