A FPGA friendly 32 bit RISC-V CPU implementation

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Working draft of the proposed RISC-V V vector extension

Functional verification project for the CORE-V family of RISC-V cores.

Simple programs (NaiveBootloader, HWTest, etc.) written in MIPS assembly